Chapter 2: Creating The Gth Ibert Core - Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual

Creating the GTH IBERT Core
Note:
This section provides a procedure to create a single Quad GTH IBERT core with integrated
SuperClock-2 controller. The procedure assumes Quad 115 and 13.0 Gb/s line rate, but
cores for any of the GTH Quads with any supported line rate can be created following the
same series of steps.
For more details on generating IBERT cores, see the Vivado Design Suite User Guide:
Programming and Debugging (UG908)
1.
2.
X-Ref Target - Figure 2-1
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
Vivado® Design Suite 2014.2 is required to rebuild the designs shown here.
Start the Vivado Design Suite.
In the Vivado window, click the Manage IP icon highlighted in
select New IP Location.
Figure 2-1: Initial Window, Vivado Design Suite
www.xilinx.com
[Ref 3].
Chapter 2
Figure 2-1, then
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