Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual page 49

11. In the new window, select Tools Run Tcl Script. In the Run Script window,
X-Ref Target - Figure 2-9
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
navigate to add_scm2.tcl in the extracted files and press OK. The SuperClock-2
Module Design Sources and Constraints are automatically added to the example
design (Figure 2-9).
Figure 2-9: Sources after Running add_scm2.tcl
www.xilinx.com 49
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