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Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual page 51

Vivado design suite 2014.2. characterization kit ibert
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13. In the Sources window, Design Sources should now reflect that the SuperClock-2
X-Ref Target - Figure 2-11
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
module is part of the example IBERT design
Figure 2-11: Design Sources File Hierarchy
www.xilinx.com
(Figure
2-11).
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