Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual page 61

7.
X-Ref Target - Figure 3-8
8.
X-Ref Target - Figure 3-9
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
In the Sources window, Design Sources should now reflect that the
SuperClock-2 module is part of the example IBERT design
Figure 3-8: Design Sources File Hierarchy
Click Run Synthesis in the Flow Navigator, which synthesizes the complete
design (Figure 3-9).
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Figure 3-9: Run Synthesis
(Figure 3-8).
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