Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual page 53

16. When the Synthesized Design opens, select dbg_hub in the Netlist window, then
X-Ref Target - Figure 2-14
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
select the Debug Core Options tab in the Cell Properties window. Change
C_USER_SCAN_CHAIN* to 2
Figure 2-14: Debug Core Options for dbg_hub
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(Figure 2-14). Click File > Save Constraints.
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