Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual page 60

Chapter 3: Creating the GTZ IBERT Core
6.
X-Ref Target - Figure 3-7
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The SuperClock-2 source code now needs to be added to the example IBERT wrapper.
Double-click ibert_7series_gtz_0_example in the Design Sources to open the
verilog code. Add the top level ports from top_scm2.v to the module declaration and
instantiate the top_scm2 module in the example IBERT wrapper
File > Save File.
Figure 3-7: SuperClock-2 in the Example IBERT Wrapper
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(Figure 3-7). Click
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014