Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual page 35

4.
X-Ref Target - Figure 1-30
VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
To view the SuperClock-2 settings in the VIO core, select the probe signal from the
Debug Probes window and drag it to the VIO-hw_vio_1 window. For example, the
frequencies, ROM addresses, and start signals are selected
Note:
The ROM address values for the Si5368 and Si570 devices (i.e., Si5368 ROM Addr and
Si570 ROM Addr) are preset to 81 to produce an output frequency of 255.000 MHz. Entering a
different ROM address changes the reference clock(s) frequency. The complete list of
pre-programmed SuperClock-2 frequencies and their associated ROM addresses is provided in
Table 1-2.
Figure 1-30: SuperClock-2 Module VIO Core
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Running the GTZ IBERT Demonstration
(Figure 1-30).
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