Viewing The Gtz Transceiver Operation; In Case Of Rx Bit Errors - Xilinx Virtex-7 FPGA VC7222 IBERT Getting Started Manual

Chapter 1: VC7222 IBERT Getting Started Guide

Viewing the GTZ Transceiver Operation

After completing
demonstration is configured and running. The link status and test settings are displayed
on the Serial IO Links tab in the Links Window shown in
Note the line rate and RX bit error count:
•
•
Note:
Status shows No Link for one or more transceivers, click the respective lane CTLE Tune button
Figure 1-33
(
X-Ref Target - Figure 1-33

In Case of RX Bit Errors

If there are initial bit errors after linking, or as a result of changing the TX or RX pattern,
click the respective BERT Reset button to zero the count.
Additional information on the Vivado Design Suite and IBERT core can be found in Vivado
Design Suite User Guide: Programming and Debugging (UG908)
Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTX Transceivers Product Guide for Vivado
Design Suite (PG132)
38
Send Feedback
step 6, page 37
The line rate for all GTZ transceivers is 28.05 Gb/s (see the Status Column in
Figure 1-33).
Verify that there are no bit errors.
External or internal CTLE tuning might be required for successful GTZ operation. If the Link
).
Figure 1-33: Serial I/O Analyzer Links
[Ref 4].
www.xilinx.com
in Starting the SuperClock-2 Module, page
Figure
VC7222 IBERT Getting Started Guide
31, the IBERT
1-33.
[Ref 3] and in LogiCORE IP
UG971 (v5.0) June 12, 2014