Gtx Quad 115 Pcie Edge Connector Connections - Xilinx KC705 User Manual

Table 1-11: PCIe Edge Connector Connections (Cont'd)
Schematic Net FPGA Pin
Name (U1)
PCIE_TX5_P U4
PCIE_TX5_N U3
PCIE_TX6_P V2
PCIE_TX6_N V1
PCIE_TX7_P Y2
PCIE_TX7_N Y1
PCIE_CLK_QO_P U8
PCIE_CLK_QO_N U7
PCIE_PRSNT_B J32 2, 4, 6
PCIE_WAKE_B F23
PCIE_PERST_B G25
Table 1-12 lists the PCIe edge connector connections for Quad 115.
Table 1-12: GTX Quad 115 PCIe Edge Connector Connections
Quad 115 Pin Name
MGTXTXP0_115_Y2
MGTXTXN0_115_Y1
MGTXRXP0_115_AA4
MGTXRXN0_115_AA3
MGTXTXP1_115_V2
MGTXTXN1_115_V1
MGTXRXP1_115_Y6
MGTXRXN1_115_Y5
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
PCIe Edge
PCIe Edge
Connector
Pin Name
Pin
A39 PERp5
A40 PERn5
A43 PERp6
A44 PERn6
A47 PERp7
A48 PERn7
A13 REFCLK+
A14 REFCLK-
A1 PRSNT#1
B11 WAKE#
A11 PERST
FPGA
Schematic Net Name
Pin (U1)
Y2 PCIE_TX7_P
Y1 PCIE_TX7_N
AA4 PCIE_RX7_P
AA3 PCIE_RX7_N
V2 PCIE_TX6_P
V1 PCIE_TX6_N
Y6 PCIE_RX6_P
Y5 PCIE_RX6_N
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Chapter 1: KC705 Evaluation Board Features
Function
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
differential clock pair from
PCIe
Integrated Endpoint block
differential clock pair from
PCIe
J42 Lane Size Select jumper
Integrated Endpoint block
wake signal, not connected
on KC705 board
Integrated Endpoint block
reset signal
PCIe Edge
PCIe Edge
Connector
Pin Name
Pin
A47 PERp7
A48 PERn7
B45 PETp7
B46 PETn7
A43 PERp6
A44 PERn6
B41 PETp6
B42 PETn6
FFG900 Placement
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y0
MGT_BANK_115
MGT_BANK_115
N/A
N/A
N/A
FFG900 Placement
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y1
38
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