Sas/Sata Backplane Functional Architecture; Figure 33. Sas/Sata Backplane Functional Block Diagram - Intel SR1500 - AXXMINIDIMM DDR-2 RAID Controller Cache Memory Manual
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Intel® Server System SR1550AL
6.4.2
SAS/SATA Backplane Functional Architecture
The figure below shows the functional blocks of the SAS/SATA backplane.
Figure 33. SAS/SATA Backplane Functional Block Diagram
6.4.2.1
Enclosure Management Controller
The backplane utilizes the features of the Vitesse* VSC410 to implement several enclosure
management functions. The chip provides in-band SAF-TE and SES management and utilizes
2
four I
C interfaces.
1. I2C bus 0 is connected to an EEPROM which stores configuration and FRU data
2. I2C bus 1 is connected to an LM75 temperature sensor
3. I2C bus 2 is connected to an IPMB bus from the server board.
4. I2C bus 3 is connected to the LSISAS1068 SAS controller.
Revision – 1.3
Intel order number D31982-006
Peripheral and Hard Drive Sub-System
47
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