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Texas Instruments TMS320x2833 series Reference Manual

Texas Instruments TMS320x2833 series Reference Manual

System control and interrupts
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TMS320x2833x, 2823x System Control and
Interrupts
Reference Guide
Literature Number: SPRUFB0C
September 2007 – Revised May 2009

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  • Page 1 TMS320x2833x, 2823x System Control and Interrupts Reference Guide Literature Number: SPRUFB0C September 2007 – Revised May 2009...
  • Page 2 SPRUFB0C – September 2007 – Revised May 2009 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Contents ..........................Preface .................. Flash and OTP Memory Blocks ....................Flash and OTP Memory ...................... 1.1.1 Flash Memory ....................... 1.1.2 OTP Memory .................... Flash and OTP Power Modes ................... 1.2.1 Flash and OTP Performance ....................1.2.2 Flash Pipeline Mode ..............1.2.3 Reserved Locations Within Flash and OTP ............
  • Page 4 www.ti.com ....................GPIO Module Overview ....................Configuration Overview ..................Digital General Purpose I/O Control ......................Input Qualification ..............4.4.1 No Synchronization (asynchronous input) ................. 4.4.2 Synchronization to SYSCLKOUT Only ............... 4.4.3 Qualification Using a Sampling Window ................GPIO and Peripheral Multiplexing (MUX) ....................

  • Page 5: List Of Figures

    www.ti.com List of Figures ..................Flash Power Mode State Diagram ....................... Flash Pipeline ................Flash Configuration Access Flow Diagram ..................Flash Options Register (FOPT) ................... Flash Power Register (FPWR) ..................Flash Status Register (FSTATUS) ................. Flash Standby Wait Register (FSTDBYWAIT) ..........
  • Page 6 www.ti.com ............4-14 GPIO Port A Qualification Control (GPACTRL) Register ............4-15 GPIO Port B Qualification Control (GPBCTRL) Register ............4-16 GPIO Port A Qualification Select 1 (GPAQSEL1) Register ............4-17 GPIO Port A Qualification Select 2 (GPAQSEL2) Register ............4-18 GPIO Port B Qualification Select 1 (GPBQSEL1) Register ............
  • Page 7 www.ti.com List of Tables ..................Flash/OTP Configuration Registers ..............Flash Options Register (FOPT) Field Descriptions ..............Flash Power Register (FPWR) Field Descriptions ..............Flash Status Register (FSTATUS) Field Descriptions ........... Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions ......Flash Standby to Active Wait Counter Register (FACTIVEWAIT) Field Descriptions ............
  • Page 8 www.ti.com ..........4-12 GPIO Port A Multiplexing 1 (GPAMUX1) Register Field Descriptions ............4-13 GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions ............4-14 GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions ............4-15 GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions ............
  • Page 9 www.ti.com ................5-16 DEVICECNF Register Field Descriptions ................... 5-17 PARTID Register Field Descriptions ..................5-18 CLASSID Register Description ..................5-19 REVID Register Field Descriptions ................5-20 PROTSTART and PROTRANGE Registers ..................... 5-21 PROTSTART Valid Values ..................... 5-22 PROTRANGE Valid Values ......................
  • Page 10 List of Tables SPRUFB0C – September 2007 – Revised May 2009 Submit Documentation Feedback...

  • Page 11: Preface

    A legend explains the notation used for the properties. – Reserved bits in a register figure designate a bit that is used for future device expansion. Related Documentation From Texas Instruments The following books describe the 2833x and related support tools that are available on the TI website: Data Manual and Errata—...
  • Page 12 Related Documentation From Texas Instruments www.ti.com SPRU566 — TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs). SPRUFB0 — TMS320x2833x, 2823x System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 2833x and 2823x digital signal controllers (DSCs).
  • Page 13 — TMS320C28x DSP/BIOS 5.32 Application Programming Interface (API) Reference Guide describes development using DSP/BIOS. Trademarks TMS320C28x, C28x, Code Composer Studio are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. SPRUFB0C – September 2007 – Revised May 2009...
  • Page 14 Read This First SPRUFB0C – September 2007 – Revised May 2009 Submit Documentation Feedback...

  • Page 15: Flash And Otp Memory Blocks

    Chapter 1 SPRUFB0C – September 2007 – Revised May 2009 Flash and OTP Memory Blocks This chapter describes the proper sequence to configure the wait states and operating mode of flash and one-time programmable (OTP) memories. It also includes information on flash and OTP power modes and how to improve flash performance by enabling the flash pipeline mode.

  • Page 16: Flash And Otp Memory

    Flash and OTP Memory www.ti.com Flash and OTP Memory This section describes how to configure flash and one-time programmable (OTP) memory. 1.1.1 Flash Memory The on-chip flash is uniformly mapped in both program and data memory space. This flash memory is always enabled and features: •...
  • Page 17 Flash and OTP Power Modes www.ti.com Note: During the boot process, the Boot ROM performs a dummy read of the Code Security Module (CSM) password locations located in the flash. This read is performed to unlock a new or erased device that has no password stored in it so that flash programming or loading of code into CSM protected SARAM can be performed.

  • Page 18: 1.2.1 Flash And Otp Performance

    Flash and OTP Power Modes www.ti.com The duration of the delay is determined by the FSTDBYWAIT and FACTIVEWAIT registers. Moving from the sleep state to a standby state is delayed by a count determined by the FSTDBYWAIT register. Moving from the standby state to the active state is delayed by a count determined by the FACTIVEWAIT register. Moving from the sleep mode (lowest power) to the active mode (highest power) is delayed by FSTDBYWAIT + FACTIVEWAIT.

  • Page 19: 1.2.3 Reserved Locations Within Flash And Otp

    Flash and OTP Power Modes www.ti.com An instruction fetch from the flash or OTP reads out 64 bits per access. The starting address of the access from flash is automatically aligned to a 64-bit boundary such that the instruction location is within the 64 bits to be fetched.

  • Page 20: 1.2.4 Procedure To Change The Flash Configuration Registers

    Flash and OTP Power Modes www.ti.com 2. For code security operation, all addresses between 0x33 FF80 and 0x33 FFF5 cannot be used for program code or data, but must be programmed to 0x0000 when the Code Security Password is programmed. If security is not a concern, addresses 0x33 FF80 through 0x33 FFF5 may be used for code or data.

  • Page 21: Flash And Otp Registers

    Flash and OTP Registers www.ti.com Flash and OTP Registers The flash and OTP memory can be configured by the registers shown in Table 1-1. The configuration registers are all EALLOW protected. The bit descriptions are in Figure 1-4 through Figure 1-10.

  • Page 22: Flash Options Register (Fopt)

    Flash and OTP Registers www.ti.com Figure 1-4. Flash Options Register (FOPT) Reserved ENPIPE R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-2. Flash Options Register (FOPT) Field Descriptions (1) (2) (3) Field Value Description 15-1 Reserved...

  • Page 23: Flash Status Register (Fstatus)

    Flash and OTP Registers www.ti.com Figure 1-6. Flash Status Register (FSTATUS) Reserved 3VSTAT R/W1C-0 Reserved ACTIVEWAITS STDBYWAITS PWRS LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset Table 1-4. Flash Status Register (FSTATUS) Field Descriptions (1) (2) Field Value...

  • Page 24: Flash Standby Wait Register (Fstdbywait)

    Flash and OTP Registers www.ti.com Figure 1-7. Flash Standby Wait Register (FSTDBYWAIT) Reserved STDBYWAIT R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-5. Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions (1) (2) Field Value Description 15-9...

  • Page 25: Flash Wait-State Register (Fbankwait)

    Flash and OTP Registers www.ti.com Figure 1-9. Flash Wait-State Register (FBANKWAIT) Reserved PAGEWAIT Reserved RANDWAIT R/W-1 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-7. Flash Wait-State Register (FBANKWAIT) Field Descriptions (1) (2) (3) Bits Field Value...

  • Page 26: Otp Wait-State Register (Fotpwait)

    Flash and OTP Registers www.ti.com Figure 1-10. OTP Wait-State Register (FOTPWAIT) Reserved OTPWAIT R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-8. OTP Wait-State Register (FOTPWAIT) Field Descriptions (1) (2) (3) Bit(s) Field Value Description 15-5...

  • Page 27: Code Security Module (Csm)

    Chapter 2 SPRUFB0C – September 2007 – Revised May 2009 Code Security Module (CSM) The code security module (CSM) is a security feature incorporated in 28x devices. It prevents access/visibility to on-chip memory to unauthorized persons—i.e., it prevents duplication/reverse engineering of proprietary code. The word secure means access to on-chip memory is protected.

  • Page 28: Functional Description

    Functional Description www.ti.com Functional Description The security module restricts the CPU access to certain on-chip memory without interrupting or stalling CPU execution. When a read occurs to a protected memory location, the read returns a zero value and CPU execution continues with the next instruction. This, in effect, blocks read and write access to various memories through the JTAG port or external peripherals.
  • Page 29 The Code Security Module ("CSM") included on this device was designed to password protect the data stored in the associated memory and is warranted by Texas Instruments (TI), in accordance with its standard terms and conditions, to conform to TI's published specifications for the warranty period applicable for this device.

  • Page 30: Csm Impact On Other On-Chip Resources

    CSM Impact on Other On-Chip Resources www.ti.com CSM Impact on Other On-Chip Resources The CSM affects access to the on-chip resources listed in Table 2-2: Table 2-2. Resources Affected by the CSM Address Block 0x00 0A80 - 0x00 0A87 Flash Configuration Registers 0x00 8000 - 0x00 8FFF L0 SARAM (4K X 16) 0x00 9000 - 0x00 9FFF...

  • Page 31: Incorporating Code Security In User Applications

    Incorporating Code Security in User Applications www.ti.com Incorporating Code Security in User Applications Code security is typically not required in the development phase of a project; however, security is needed once a robust code is developed. Before such a code is programmed in the flash memory, a password should be chosen to secure the device.

  • Page 32: 2.3.1 Environments That Require Security Unlocking

    Incorporating Code Security in User Applications www.ti.com Figure 2-1. CSM Status and Control Register (CSMSCR) FORCESEC Reserved Reserved SECURE R/W-1 R-10111 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-5. CSM Status and Control Register (CSMSCR) Field Descriptions Bits Field Value...

  • Page 33: 2.3.2 Password Match Flow

    Incorporating Code Security in User Applications www.ti.com 2.3.2 Password Match Flow Password match flow (PMF) is essentially a sequence of eight dummy reads from password locations (PWL) followed by eight writes to KEY registers. Figure 2-2 shows how the PMF helps to initialize the security logic registers and disable security logic. Figure 2-2.

  • Page 34: 2.3.3 Unsecuring Considerations For Devices With/Without Code Security

    Incorporating Code Security in User Applications www.ti.com 2.3.3 Unsecuring Considerations for Devices With/Without Code Security Case 1 and Case 2 provide unsecuring considerations for devices with and without code security. Case 1: Device With Code Security A device with code security should have a predetermined password stored in the password locations (0x33 FFF8 - 0x33 FFFF in memory).
  • Page 35 Incorporating Code Security in User Applications www.ti.com 2.3.3.1 C Code Example to Unsecure volatile int *CSM = (volatile int *)0x000AE0; //CSM register file volatile int *PWL = (volatile int *)0x0033FFF8; //Password location volatile int tmp; int I; // Read the 128-bits of the password locations (PWL) // in flash at address 0x33 FFF8 - 0x33 FFFF // If the device is secure, then the values read will // not actually be loaded into the temp variable, so...

  • Page 36: Do's And Don'ts To Protect Security Logic

    Do's and Don'ts to Protect Security Logic www.ti.com Do's and Don'ts to Protect Security Logic 2.4.1 Do's • To keep the debug and code development phase simple, use the device in the unsecure mode; i.e., use all 128 bits as ones in the password locations (or use a password that is easy to remember). Use a password after the development phase when the code is frozen.

  • Page 37: Clocking

    Chapter 3 SPRUFB0C – September 2007 – Revised May 2009 Clocking This section describes the oscillator, PLL and clocking mechanisms, the watchdog function, and the low-power modes....................Topic Page ............. Clocking and System Control ..............OSC and PLL Block ............

  • Page 38: Clocking And System Control

    Clocking and System Control www.ti.com Clocking and System Control Figure 3-1 shows the various clock and reset domains. The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-1. Figure 3-1. Clock and Reset Domains C28x Core CLKIN SYSCLKOUT...

  • Page 39: Peripheral Clock Control 0 Register (Pclkcr0)

    Clocking and System Control www.ti.com Table 3-1. PLL, Clocking, Watchdog, and Low-Power Mode Registers Name Address Size Description Bit Description (x16) PLLSTS 0x7011 PLL Status Register Figure 3-12 HISPCP 0x701A High-Speed Peripheral Clock (HSPCLK) Prescaler Register Figure 3-5 LOSPCP 0x701B Low-Speed Peripheral Clock (LSPCLK) Prescaler Register Figure 3-6 PCLKCR0...

  • Page 40: Peripheral Clock Control 1 Register (Pclkcr1)

    Clocking and System Control www.ti.com Table 3-2. Peripheral Clock Control 0 Register (PCLKCR0) Field Descriptions (continued) Field Valu Description MCBSPAENCLK McBSP-A Clock Enable The McBSP-A module is not clocked. (default) The McBSP-A module is clocked by the low-speed clock (LSPCLK). SCIBENCLK SCI-B clock enable SCI-B module is not clocked.

  • Page 41: Peripheral Clock Control 1 Register (Pclkcr1) Field Descriptions

    Clocking and System Control www.ti.com Table 3-3. Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions Bits Field Value Description EQEP2ENCLK eQEP2 clock enable The eQEP2 module is not clocked. (default) The eQEP2 module is clocked by the system clock (SYSCLKOUT). EQEP1ENCLK eQEP1 clock enable The eQEP1 module is not clocked.
  • Page 42 Clocking and System Control www.ti.com Table 3-3. Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions (continued) Bits Field Value Description EPWM1ENCLK ePWM1 clock enable. The ePWM1 module is not clocked. (default) The ePWM1 module is clocked by the system clock (SYSCLKOUT). Clocking SPRUFB0C –...

  • Page 43: Peripheral Clock Control 3 Register (Pclkcr3)

    Clocking and System Control www.ti.com Figure 3-4. Peripheral Clock Control 3 Register (PCLKCR3) Reserved GPIOINENCLK XINTFENCLK DMAENCLK CPUTIMER2ENCLK CPUTIMER1ENCLK CPUTIMER0ENCLK R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-4.

  • Page 44: High-Speed Peripheral Clock Prescaler (Hispcp) Register

    Clocking and System Control www.ti.com Figure 3-5. High-Speed Peripheral Clock Prescaler (HISPCP) Register Reserved HSPCLK R/W-001 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-5. High-Speed Peripheral Clock Prescaler (HISPCP) Field Descriptions Bits Field Value Description 15-3...

  • Page 45: Osc And Pll Block

    OSC and PLL Block www.ti.com OSC and PLL Block The on-chip oscillator and phase-locked loop (PLL) block provides the clocking signals for the device, as well as control for low-power mode (LPM) entry. 3.2.1 PLL-Based Clock Module The 2833x, 2823x devices have an on-chip, PLL-based clock module. The PLL has a 4-bit ratio control to select different CPU clock rates.

  • Page 46: 3.2.2 Main Oscillator Fail Detection

    OSC and PLL Block www.ti.com Table 3-7. Possible PLL Configuration Modes PLL Mode Remarks PLLSTS[DIVSEL] SYSCLKOUT PLL Off Invoked by the user setting the PLLOFF bit in the PLLSTS register. The 0, 1 OSCCLK/4 PLL block is disabled in this mode. This can be useful to reduce system OSCCLK/2 noise and for low power operation.
  • Page 47 OSC and PLL Block www.ti.com If the OSCCLK input signal is missing, then the PLL will output a default "limp mode" frequency and the VCOCLK counter will continue to increment. Since the OSCCLK signal is missing, the OSCCLK counter will not increment and, therefore, the VCOCLK counter is not periodically cleared. Eventually, the VCOCLK counter overflows and, if required, the device switches the CLKIN input to the CPU to the limp mode output frequency of the PLL.

  • Page 48: 3.2.3 Xclkout Generation

    OSC and PLL Block www.ti.com The following list describes the behavior of the missing clock detect logic in various operating modes: • PLL by-pass mode When the PLL control register is set to 0x0000, the PLL is by-passed. Depending on the state of the PLLSTS[DIVSEL] bit, OSCCLK, OSCCLK/2, or OSCCLK/4 is connected directly to the CPU's input clock, CLKIN.

  • Page 49: 3.2.4 Pll Control (Pllcr) Register

    OSC and PLL Block www.ti.com 3.2.4 PLL Control (PLLCR) Register The PLLCR register is used to change the PLL multiplier of the device. Before writing to the PLLCR register, the following requirements must be met: • The PLLSTS[DIVSEL] bit must be 0 (CLKIN divide by 4 enabled). Change PLLSTS[DIVSEL] to 1 only after the PLL has completed locking, i.e., after PLLSTS[PLLLOCKS] = 1.

  • Page 50: Pllcr Change Procedure Flow Chart

    OSC and PLL Block www.ti.com Figure 3-10. PLLCR Change Procedure Flow Chart Start Device is operating in limp PLLSTS[MCLKSTS] mode. Take appropriate = 1? action for your system. Do not write to PLLCR. PLLSTS[DIVSEL] Set PLLSTS[DIVSEL] = 0 = 2 or 3? Set PLLSTS[MCLKOFF] = 1 to disable failed oscillator detect logic...

  • Page 51: 3.2.5 Pll Control, Status And Xclkout Register Descriptions

    OSC and PLL Block www.ti.com 3.2.5 PLL Control, Status and XCLKOUT Register Descriptions The DIV field in the PLLCR register controls whether the PLL is bypassed or not and sets the PLL clocking ratio when it is not bypassed. PLL bypass is the default mode after reset. Do not write to the DIV field if the PLLSTS[DIVSEL] bit is 10 or 01, or if the PLL is operating in limp mode as indicated by the PLLSTS[MCLKSTS] bit being set.

  • Page 52: 3.2.6 External Reference Oscillator Clock Option

    OSC and PLL Block www.ti.com Table 3-9. PLL Status Register (PLLSTS) Field Descriptions (continued) (1) (2) Bits Field Value Description Select Divide By 8 for CLKIN 00, 01 Select Divide By 4 for CLKIN Select Divide By 2 for CLKIN Select Divide By 1 for CLKIN.

  • Page 53: Low-Power Modes Block

    Low-Power Modes Block www.ti.com Low-Power Modes Block Table 3-10 summarizes the various modes. The various low-power modes operate as shown in Table 3-11. See the TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, TMS320F28232 Digital Signal Controllers (DSCs) Data Manual (literature number SPRS439) for exact timing for entering and exiting the low power modes.

  • Page 54: Low Power Mode Control 0 Register (Lpmcr0)

    Low-Power Modes Block www.ti.com Table 3-11. Low Power Modes (continued) Mode Description HALT If the LPM bits in the LPMCR0 register are set to 1x, the device enters the HALT mode when the IDLE Mode: instruction is executed. In HALT mode all of the device clocks, including the PLL and oscillator, are shut down. Before entering the HALT mode, you should perform the following tasks: •...

  • Page 55: Watchdog Block

    Watchdog Block www.ti.com Table 3-12. Low Power Mode Control 0 Register (LPMCR0) Field Descriptions (continued) Bits Field Value Description These bits set the low power mode for the device. Set the low power mode to IDLE (default) Set the low power mode to STANDBY Set the low power mode to HALT Set the low power mode to HALT The low power mode bits (LPM) only take effect when the IDLE instruction is executed.

  • Page 56: 3.4.1 Servicing The Watchdog Timer

    Watchdog Block www.ti.com 3.4.1 Servicing The Watchdog Timer The WDCNTR is reset when the proper sequence is written to the WDKEY register before the 8-bit watchdog counter (WDCNTR) overflows. The WDCNTR is reset-enabled when a value of 0x55 is written to the WDKEY.

  • Page 57: 3.4.3 Watchdog Operation In Low Power Modes

    Watchdog Block www.ti.com 3.4.3 Watchdog Operation in Low Power Modes In STANDBY mode, all of the clocks to the peripherals are turned off on the device. The only peripheral that remains functional is the watchdog since the watchdog module runs off the oscillator clock (OSCCLK).

  • Page 58: 3.4.5 Watchdog Registers

    Watchdog Block www.ti.com 3.4.5 Watchdog Registers The system control and status register (SCSR) contains the watchdog override bit and the watchdog interrupt enable/disable bit. Figure 3-15 describes the bit functions of the SCSR register. Figure 3-15. System Control and Status Register (SCSR) Reserved Reserved WDINTS...

  • Page 59: Watchdog Counter Register (Wdcntr)

    Watchdog Block www.ti.com Figure 3-16. Watchdog Counter Register (WDCNTR) Reserved WDCNTR LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-15. Watchdog Counter Register (WDCNTR) Field Descriptions Bits Field Description 15-8 Reserved Reserved WDCNTR These bits contain the current value of the WD counter. The 8-bit counter continually increments at the watchdog clock (WDCLK), rate.

  • Page 60: 32-Bit Cpu Timers 0/1/2

    32-Bit CPU Timers 0/1/2 www.ti.com Table 3-17. Watchdog Control Register (WDCR) Field Descriptions (continued) Bits Field Value Description WDDIS Watchdog disable. On reset, the watchdog module is enabled. Enables the watchdog module. WDDIS can be modified only if the WDOVERRIDE bit in the SCSR register is set to 1.

  • Page 61: Cpu-Timer Interrupts Signals And Output Signal

    32-Bit CPU Timers 0/1/2 www.ti.com Figure 3-20. CPU-Timer Interrupts Signals and Output Signal INT1 TINT0 CPU-TIMER 0 INT12 TINT1 CPU-TIMER 1 INT13 XINT13 TINT2 CPU-TIMER 2 INT14 (Reserved for DSP/BIOS) The timer registers are connected to the Memory Bus of the 28x processor. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.

  • Page 62: Timerxtim Register (X = 0, 1, 2)

    32-Bit CPU Timers 0/1/2 www.ti.com Figure 3-21. TIMERxTIM Register (x = 0, 1, 2) R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-19. TIMERxTIM Register Field Descriptions Bits Field Description 15-0 CPU-Timer Counter Registers (TIMH:TIM): The TIM register holds the low 16 bits of the current 32-bit count of the timer.

  • Page 63: Timerxtcr Register (X = 0, 1, 2)

    32-Bit CPU Timers 0/1/2 www.ti.com Table 3-22. TIMERxPRDH Register Field Descriptions Bits Field Description 15-0 PRDH See description for TIMERxPRD Figure 3-25. TIMERxTCR Register (x = 0, 1, 2) Reserved FREE SOFT Reserved R/W-0 R/W-0 R/W-0 R/W-0 Reserved Reserved R/W-0 R/W-0 LEGEND: R/W = Read/Write;...

  • Page 64: Timerxtpr Register (X = 0, 1, 2)

    32-Bit CPU Timers 0/1/2 www.ti.com Table 3-23. TIMERxTCR Register Field Descriptions (continued) Bits Field Value Description Reserved Reserved Figure 3-26. TIMERxTPR Register (x = 0, 1, 2) TDDR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-24.

  • Page 65: General-Purpose Input/Output (Gpio)

    Chapter 4 SPRUFB0C – September 2007 – Revised May 2009 General-Purpose Input/Output (GPIO) The GPIO multiplexing (MUX) registers are used to select the operation of shared pins. The pins are named by their general purpose I/O name (i.e., GPIO0 - GPIO87). These pins can be individually selected to operate as digital I/O, referred to as GPIO, or connected to one of up to three peripheral I/O signals (via the GPxMUXn registers).

  • Page 66: Gpio Module Overview

    GPIO Module Overview www.ti.com GPIO Module Overview Up to three independent peripheral signals are multiplexed on a single GPIO-enabled pin in addition to individual pin bit-I/O capability. There are three 32-bit I/O ports. Port A consists of GPIO0-GPIO31, port B consists of GPIO32-GPIO63, and port C consists of GPIO64-87.

  • Page 67: Gpio28 To Gpio31 Multiplexing Diagram (Peripheral 2 And Peripheral 3 Outputs Merged)

    GPIO Module Overview www.ti.com Figure 4-2. GPIO28 to GPIO31 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) GPIOLPMSEL LPMCR0 GPIO XINT1SEL Low Power Modes Block GPIO XINT2SEL GPIOXNMISEL GPIOx.async External interrupt GPAPUD SYSCLKOUT 0 = enable PU 1 = disable PU GPADAT (read) (disabled after reset) (default on reset)

  • Page 68: Gpio32, Gpio33 Multiplexing Diagram

    GPIO Module Overview www.ti.com Figure 4-3. GPIO32, GPIO33 Multiplexing Diagram GPIO XINT3SEL GPIO XINT4SEL GPIO XINT5SEL GPIO XINT6SEL GPIO XINT7SEL External interrupt GPBPUD SYSCLKOUT 0 = enable PU 1 = disable PU GPBDAT (read) (disabled after reset) (default on reset) Sync (async disable 3 samples...

  • Page 69: Gpio34 To Gpio63 Multiplexing Diagram (Peripheral 2 And Peripheral 3 Outputs Merged)

    GPIO Module Overview www.ti.com Figure 4-4. GPIO34 to GPIO63 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) GPIO XINT3SEL GPIO XINT4SEL GPIO XINT5SEL GPIO XINT6SEL GPIO XINT7SEL External interrupt GPBDAT (read) GPBPUD SYSCLKOUT XINT Input Signals 0 = enable PU (XREADY, XD31:16_IN) 1 = disable PU (disabled after reset)

  • Page 70: Gpio64 To Gpio79 Multiplexing Diagram (Minimal Gpios Without Qualification)

    GPIO Module Overview www.ti.com Figure 4-5. GPIO64 to GPIO79 Multiplexing Diagram (Minimal GPIOs Without Qualification) GPCPUD SYSCLKOUT 0 = enable PU 1 = disable PU (disabled after reset) GPIOx_IN Sync GPCDAT (read) (async disable when low) async GPIO64 XD0_IN/../XD15_IN GPIO79 Pins GPCSET, GPCCLEAR,...

  • Page 71: Configuration Overview

    Configuration Overview www.ti.com Configuration Overview The pin function assignments, input qualification, and the external interrupt (XINT1 – XINT7, XNMI) sources are all controlled by the GPIO configuration control registers. In addition, you can assign pins to wake the device from the HALT and STANDBY low power modes and enable/disable internal pullup resistors.

  • Page 72: Digital General Purpose I/O Control

    Digital General Purpose I/O Control www.ti.com To plan configuration of the GPIO module, consider the following steps: Step 1. Plan the device pin-out: Through a pin multiplexing scheme, a lot of flexibility is provided for assigning functionality to the GPIO-capable pins. Before getting started, look at the peripheral options available for each pin, and plan pin-out for your specific system.

  • Page 73: Gpio Data Registers

    Digital General Purpose I/O Control www.ti.com Table 4-3. GPIO Data Registers Name Address Size (x16) Register Description Bit Description GPADAT 0x6FC0 GPIO A Data Register (GPIO0-GPIO31) Figure 4-26 GPASET 0x6FC2 GPIO A Set Register (GPIO0-GPIO31) Figure 4-29 GPACLEAR 0x6FC4 GPIO A Clear Register (GPIO0-GPIO31) Figure 4-29 GPATOGGLE 0x6FC6...

  • Page 74: Input Qualification

    Input Qualification www.ti.com Writing a 0 to any bit in the toggle registers has no effect. Input Qualification The input qualification scheme has been designed to be very flexible. You can select the type of input qualification for each GPIO pin by configuring the GPAQSEL1, GPAQSEL2, GPBQSEL1 and GPBQSEL2 registers.

  • Page 75: Sampling Period

    Input Qualification www.ti.com Time between samples (sampling period): To qualify the signal, the input signal is sampled at a regular period. The sampling period is specified by the user and determines the time duration between samples, or how often the signal will be sampled, relative to the CPU clock (SYSCLKOUT).

  • Page 76: Case 1: Three-Sample Sampling Window Width

    Input Qualification www.ti.com Number of samples: The number of times the signal is sampled is either 3 samples or 6 samples as specified in the qualification selection (GPAQSEL1, GPAQSEL2, GPBQSEL1, and GPBQSEL2) registers. When 3 or 6 consecutive cycles are the same, then the input change will be passed through to the DSP. Total Sampling Window Width: The sampling window is the time during which the input signal will be sampled as shown in Figure...

  • Page 77: Input Qualifier Clock Cycles

    Input Qualification www.ti.com Example Qualification Window: For the example shown in Figure 4-7, the input qualification has been configured as follows: • GPxQSEL1/2 = 1,0. This indicates a six-sample qualification. • GPxCTRL[QUALPRDn] = 1. The sampling period is t (SP) = 2 × GPxCTRL[QUALPRDn] × T SYSCLKOUT This configuration results in the following: •...

  • Page 78: Gpio And Peripheral Multiplexing (Mux)

    GPIO and Peripheral Multiplexing (MUX) www.ti.com GPIO and Peripheral Multiplexing (MUX) Up to three different peripheral functions are multiplexed along with a general input/output (GPIO) function per pin. This allows you to pick and choose a peripheral mix that will work best for the particular application.

  • Page 79: Default State Of Peripheral Input

    GPIO and Peripheral Multiplexing (MUX) www.ti.com Table 4-8. Default State of Peripheral Input Peripheral Input Description Default Input TZ1-TZ6 Trip zone 1-6 EPWMSYNCI ePWM Synch Input ECAPn eCAP input EQEPnA eQEP input EQEPnI eQEP index EQEPnS eQEP strobe SPICLKx SPI clock SPISTEx SPI transmit enable SPISIMOx...

  • Page 80: Gpioa Mux

    GPIO and Peripheral Multiplexing (MUX) www.ti.com Table 4-9. GPIOA MUX Default at Reset Primary I/O Function Peripheral Selection Peripheral Selection 2 Peripheral Selection 3 GPAMUX1 Register (GPAMUX1 bits = 00) (GPAMUX1 bits = 01) (GPAMUX1 bits = 10) (GPAMUX1 bits = 11) Bits GPIO0 EPWM1A (O)

  • Page 81: Gpiob Mux

    GPIO and Peripheral Multiplexing (MUX) www.ti.com Table 4-10. GPIOB MUX Default at Reset Primary I/O Function Peripheral Selection 1 Peripheral Selection 2 Peripheral Selection 3 GPBMUX1 Register (GPBMUX1 bits = 00) (GPBMUX1 bits = 01) (GPBMUX1 bits = 10) (GPBMUX1 bits = 11) Bits GPIO32 (I/O) SDAA (I/OC)

  • Page 82: Gpioc Mux

    GPIO and Peripheral Multiplexing (MUX) www.ti.com Table 4-11. GPIOC MUX Default at Reset Primary I/O Function Peripheral Selection 2 or 3 GPCMUX1 Register Bits (GPCMUX1 bits = 00 or 01) (GPCMUX1 bits = 10 or 11) GPIO64 (I/O) XD15 (I/O) GPIO65 (I/O) XD14 (I/O) GPIO66 (I/O)

  • Page 83: Register Bit Definitions

    Register Bit Definitions www.ti.com Register Bit Definitions Figure 4-8. GPIO Port A MUX 1 (GPAMUX1) Register GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 R/W-0 R/W-0 R/W-0...
  • Page 84 Register Bit Definitions www.ti.com Table 4-12. GPIO Port A Multiplexing 1 (GPAMUX1) Register Field Descriptions (continued) Bits Field Value Description 23-22 GPIO11 Configure the GPIO11 pin as: GPIO11 - General purpose I/O 11 (default) (I/O) EPWM6B - ePWM 6 output B (O) SCIRXDB - SCI-B receive (I) ECAP4 - eCAP4.

  • Page 85: Gpio Port A Mux 2 (Gpamux2) Register

    Register Bit Definitions www.ti.com Table 4-12. GPIO Port A Multiplexing 1 (GPAMUX1) Register Field Descriptions (continued) Bits Field Value Description GPIO2 Configure the GPIO2 pin as: GPIO2 (I/O) General purpose I/O 2 (default) (I/O) EPWM2A - ePWM2 output A (O) Reserved.
  • Page 86 Register Bit Definitions www.ti.com Table 4-13. GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions (continued) Bits Field Value Description 23-22 GPIO27 Configure the GPIO27 pin as: GPIO27 - General purpose I/O 27 (default) (I/O) ECAP4 - eCAP4. (I/O) EQEP2S - eQEP2 strobe (I/O) MFSXB - McBSP-B Transmit Frame Synch (I/O) 21-20 GPIO26...

  • Page 87: Gpio Port B Mux 1 (Gpbmux1) Register

    Register Bit Definitions www.ti.com Table 4-13. GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions (continued) Bits Field Value Description GPIO18 Configure the GPIO18 pin as: GPIO18 - General purpose I/O 18 (default) (I/O) SPICLKA - SPI-A clock (I/O) SCITXDB - SCI-B transmit. (O) CANRXA - eCAN-A Receive (I) GPIO17 Configure the GPIO17 pin as:...
  • Page 88 Register Bit Definitions www.ti.com Table 4-14. GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions (continued) Field Value Description 25:24 GPIO44 Configure this pin: GPIO 44 - general purpose I/O 44 (default) Reserved 10 or XA4 - External interface (XINTF) address line 4 (O) 23:22 GPIO43 Configure this pin as:...

  • Page 89: Gpio Port B Mux 2 (Gpbmux2) Register

    Register Bit Definitions www.ti.com Table 4-14. GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions (continued) Field Value Description GPIO34 Configure this pin as: GPIO 34 - general purpose I/O 34 (default) ECAPI - Enhanced capture input/output 1 (I/O) 10 or XREADY - External interface ready signal GPIO33 Configure this pin as:...
  • Page 90 Register Bit Definitions www.ti.com Table 4-15. GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions (continued) Field Value Description 23:22 GPIO59 Configure this pin as: GPIO 59 - general purpose I/O 59 (default) MFSRA - McBSP-A receive frame synch (I/O) 10 or XD20 - External interface data line 20 (I/O) 21:20...

  • Page 91: Gpio Port C Mux 1 (Gpcmux1) Register

    Register Bit Definitions www.ti.com Table 4-15. GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions (continued) Field Value Description GPIO49 Configure this pin as: GPIO 49 - general purpose I/O 49 (default) ECAP6 - Enhanced Capture input/output 6 (I/O) 10 or XD30 - External interface data line 30 (I/O) GPIO48 Configure this pin as:...

  • Page 92: Gpio Port C Mux 2 (Gpcmux2) Register

    Register Bit Definitions www.ti.com Table 4-16. GPIO Port C MUX 1 (GPCMUX1) Register Field Descriptions (continued) Field Value Description 15:14 GPIO71 Configure this pin as: 00 or 01 GPIO 71 - general purpose I/O 71 (default) 10 or 11 XD8 - External interface data line 8 (O) 13:12 GPIO70 Configure this pin as:...
  • Page 93 Register Bit Definitions www.ti.com Table 4-17. GPIO Port C MUX 2 (GPCMUX2) Register Field Descriptions (continued) Field Value Description 13:12 GPIO86 Configure this pin as: 00 or GPIO 86 - general purpose I/O 86 (default) 10 or XA14 - External interface address line 14 (O) 11:10 GPIO85 Configure this pin as:...

  • Page 94: Gpio Port A Qualification Control (Gpactrl) Register

    Register Bit Definitions www.ti.com Figure 4-14. GPIO Port A Qualification Control (GPACTRL) Register QUALPRD3 QUALPRD2 R/W-0 R/W-0 QUALPRD1 QUALPRD0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset The GPxCTRL registers specify the sampling period for input pins when configured for input qualification using a window of 3 or 6 samples.

  • Page 95: Gpio Port B Qualification Control (Gpbctrl) Register

    Register Bit Definitions www.ti.com Figure 4-15. GPIO Port B Qualification Control (GPBCTRL) Register QUALPRD3 QUALPRD2 R/W-0 R/W-0 QUALPRD1 QUALPRD0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-19. GPIO Port B Qualification Control (GPBCTRL) Register Field Descriptions Bits Field Value...

  • Page 96: Gpio Port A Qualification Select 1 (Gpaqsel1) Register

    Register Bit Definitions www.ti.com Figure 4-16. GPIO Port A Qualification Select 1 (GPAQSEL1) Register GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0...

  • Page 97: Gpio Port B Qualification Select 1 (Gpbqsel1) Register

    Register Bit Definitions www.ti.com Figure 4-18. GPIO Port B Qualification Select 1 (GPBQSEL1) Register GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0...

  • Page 98: Gpio Port A Direction (Gpadir) Register

    Register Bit Definitions www.ti.com The GPADIR and GPBDIR registers control the direction of the pins when they are configured as a GPIO in the appropriate MUX register. The direction register has no effect on pins configured as peripheral functions. Figure 4-20. GPIO Port A Direction (GPADIR) Register GPIO31 GPIO30 GPIO29...

  • Page 99: Gpio Port C Direction (Gpcdir) Register

    Register Bit Definitions www.ti.com Table 4-25. GPIO Port B Direction (GPBDIR) Register Field Descriptions Bits Field Value Description 31-0 GPIO63-GPIO32 Controls direction of GPIO pin when GPIO mode is selected. Reading the register returns the current value of the register setting Configures the GPIO pin as an input.

  • Page 100: Gpio Port A Pullup Disable (Gpapud) Registers

    Register Bit Definitions www.ti.com Figure 4-23. GPIO Port A Pullup Disable (GPAPUD) Registers GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0...

  • Page 101: Gpio Port C Pullup Disable (Gpcpud) Registers

    Register Bit Definitions www.ti.com Figure 4-25. GPIO Port C Pullup Disable (GPCPUD) Registers Reserved R/W-0 GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72 R/W-0 R/W-0 R/W-0 R/W-0...

  • Page 102: Gpio Port B Data (Gpbdat) Register

    Register Bit Definitions www.ti.com Table 4-30. GPIO Port A Data (GPADAT) Register Field Descriptions Bits Field Value Description 31-0 GPIO31-GPIO0 Each bit corresponds to one GPIO port A pin (GPIO0-GPIO31) as shown in Figure 4-26. Reading a 0 indicates that the state of the pin is currently low, irrespective of the mode the pin is configured for.

  • Page 103: Gpio Port C Data (Gpcdat) Register

    Register Bit Definitions www.ti.com Figure 4-28. GPIO Port C Data (GPCDAT) Register Reserved GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x...

  • Page 104: Gpio Port A Set, Clear And Toggle (Gpaset, Gpaclear, Gpatoggle) Registers

    Register Bit Definitions www.ti.com Figure 4-29. GPIO Port A Set, Clear and Toggle (GPASET, GPACLEAR, GPATOGGLE) Registers GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 R/W-0 R/W-0...

  • Page 105: Gpio Port B Set, Clear And Toggle (Gpbset, Gpbclear, Gpbtoggle) Registers

    Register Bit Definitions www.ti.com Figure 4-30. GPIO Port B Set, Clear and Toggle (GPBSET, GPBCLEAR, GPBTOGGLE) Registers GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48 R/W-x R/W-x...

  • Page 106: Gpio Port C Set, Clear And Toggle (Gpcset, Gpcclear, Gpctoggle) Registers

    Register Bit Definitions www.ti.com Figure 4-31. GPIO Port C Set, Clear and Toggle (GPCSET, GPCCLEAR, GPCTOGGLE) Registers Reserved GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72 R/W-0...

  • Page 107: Gpio Xintn, Xnmi Interrupt Select (Gpioxintnsel, Gpioxnmisel) Registers

    Register Bit Definitions www.ti.com Figure 4-32. GPIO XINTn, XNMI Interrupt Select (GPIOXINTnSEL, GPIOXNMISEL) Registers Reserved GPIOXINTnSEL R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-42. GPIO XINTn Interrupt Select (GPIOXINTnSEL) Register Field Descriptions Bits Field Value...

  • Page 108: Gpio Low Power Mode Wakeup Select (Gpiolpmsel) Register

    Register Bit Definitions www.ti.com Table 4-46. GPIO XNMI Interrupt Select (GPIOXNMISEL) Register Field Descriptions Bits Field Value Description 15-5 Reserved Reserved GPIOSEL Select which port A GPIO signal (GPIO0 - GPIO31) will be used as the XNMI interrupt source. In addition you can configure the interrupt in the XNMICR register described in Section 6.6.

  • Page 109: Peripheral Frames

    Chapter 5 SPRUFB0C – September 2007 – Revised May 2009 Peripheral Frames This chapter describes the peripheral frames. It also describes the device emulation registers....................Topic Page ............Peripheral Frame Registers ........... EALLOW-Protected Registers ............Device Emulation Registers ........... Write-Followed-by-Read Protection SPRUFB0C –...

  • Page 110: Peripheral Frame Registers

    Peripheral Frame Registers www.ti.com Peripheral Frame Registers The 2833x, 2823x devices contain four peripheral register spaces. The spaces are categorized as follows: • Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 5-1.

  • Page 111: Peripheral Frame 2 Registers

    Peripheral Frame Registers www.ti.com Table 5-2. Peripheral Frame 1 Registers (continued) Name Address Range Size (x16) Access Type GPIO Control Registers 0x6F80 - 0x6FBF EALLOW-protected GPIO Data Registers 0x6FC0 - 0x6FDF Not EALLOW-protected GPIO Interrupt and LPM Select 0x6FE0 - 0x6FFF EALLOW-protected Registers Table 5-3.

  • Page 112: Eallow-Protected Registers

    EALLOW-Protected Registers www.ti.com EALLOW-Protected Registers Several control registers are protected from spurious CPU writes by the EALLOW protection mechanism. The EALLOW bit in status register 1 (ST1) indicates if the state of protection as shown in Table 5-5. Table 5-5. Access to EALLOW-Protected Registers EALLOW Bit CPU Writes CPU Reads...

  • Page 113: Eallow-Protected Code Security Module (Csm) Registers

    EALLOW-Protected Registers www.ti.com Table 5-8. EALLOW-Protected Code Security Module (CSM) Registers Size Register Name Address Register Description (x16) KEY0 0x0AE0 Low word of the 128-bit KEY register KEY1 0x0AE1 Second word of the 128-bit KEY register KEY2 0x0AE2 Third word of the 128-bit KEY register KEY3 0x0AE3 Fourth word of the 128-bit KEY register...

  • Page 114: Eallow-Protected Pll, Clocking, Watchdog, And Low-Power Mode Registers

    EALLOW-Protected Registers www.ti.com Table 5-10. EALLOW-Protected PLL, Clocking, Watchdog, and Low-Power Mode Registers Name Address Size Description (x16) PLLSTS 0x7011 PLL Status Register HISPCP 0x701A High-Speed Peripheral Clock Prescaler Register for HSPCLK Clock LOSPCP 0x701B Low-Speed Peripheral Clock Prescaler Register for HSPCLK Clock PCLKCR0 0x701C Peripheral Clock Control Register 0...

  • Page 115: Eallow-Protected Ecan Registers

    EALLOW-Protected Registers www.ti.com Table 5-12. EALLOW-Protected eCAN Registers Name eCAN-A eCAN-B Size (x16) Description Address Address CANMC 0x6014 0x6214 Master Control Register CANBTC 0x6016 0x6216 Bit Timing Configuration Register CANGIM 0x6020 0x6220 Global Interrupt Mask Register CANMIM 0x6024 0x6224 Mailbox Interrupt Mask Register CANTSC 0x602E 0x622E...

  • Page 116: Device Emulation Registers

    Device Emulation Registers www.ti.com Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 5-15. Table 5-15. Device Emulation Registers Name Address Size (x16) Description...

  • Page 117: Part Id Register

    Device Emulation Registers www.ti.com Figure 5-2. Part ID Register PARTTYPE PARTNO LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-17. PARTID Register Field Descriptions Field Value Description 15:8 PARTTYPE These 8 bits specify the type of device such as flash-based. 0x00 Flash-based device All other values are reserved.

  • Page 118: Write-Followed-By-Read Protection

    Write-Followed-by-Read Protection www.ti.com Table 5-19. REVID Register Field Descriptions Bits Field Value Description 15-0 REVID These 16 bits specify the silicon revision number for the particular part. This number always starts with 0x0000 on the first revision of the silicon and is incremented on any subsequent revisions.

  • Page 119: Protrange Valid Values

    Write-Followed-by-Read Protection www.ti.com Table 5-22. PROTRANGE Valid Values Register Bits Block Size Register Value 0x0000 0x0001 0x0003 0x0007 0x000F 256K 0x0FFF 512K 0x1FFF 0x3FFF 0x7FFF 0xFFFF Not all register values are valid. The PROTSTART address value must be a multiple of the range value. For example: if the block size is set to 4K, then the start address can only be at any 4K boundary.
  • Page 120 Peripheral Frames SPRUFB0C – September 2007 – Revised May 2009 Submit Documentation Feedback...

  • Page 121: Peripheral Interrupt Expansion (Pie)

    Chapter 6 SPRUFB0C – September 2007 – Revised May 2009 Peripheral Interrupt Expansion (PIE) The peripheral interrupt expansion (PIE) block multiplexes numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support 96 individual interrupts that are grouped into blocks of eight. Each group is fed into one of 12 core interrupt lines (INT1 to INT12).

  • Page 122: Overview Of The Pie Controller

    Overview of the PIE Controller www.ti.com Overview of the PIE Controller The 28x CPU supports one nonmaskable interrupt (NMI) and 16 maskable prioritized interrupt requests (INT1-INT14, RTOSINT, and DLOGINT) at the CPU level. The 28x devices have many peripherals and each peripheral is capable of generating one or more interrupts in response to many events at the peripheral level.
  • Page 123 Overview of the PIE Controller www.ti.com the request directly to the CPU. For multiplexed interrupt sources, each interrupt group in the PIE block has an associated flag register (PIEIFRx) and enable (PIEIERx) register (x = PIE group 1 - PIE group 12). Each bit, referred to as y, corresponds to one of the 8 MUXed interrupts within the group.

  • Page 124: Typical Pie/Cpu Interrupt Response - Intx.y

    Overview of the PIE Controller www.ti.com Figure 6-2. Typical PIE/CPU Interrupt Response - INTx.y Start Stage E IFRx bit set 1 Stage A Wait for any PIEIFRx.y=1 PIEIFRx.y=1 Stage F IERx bit=1 Stage B Wait for Stage G PIEIERx.y=1 PIEIERx.y=1 INTM bit=0 Stage H CPU responds...

  • Page 125: Vector Table Mapping

    Vector Table Mapping www.ti.com The CPU then prepares to service the interrupt. This preparation process is described in detail in TMS320C28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430). In preparation, the corresponding CPU IFR and IER bits are cleared, EALLOW and LOOP are cleared, INTM and DBGM are set, the pipeline is flushed and the return address is stored, and the automatic context save is performed.

  • Page 126: Reset Flow Diagram

    Vector Table Mapping www.ti.com After the reset and boot is complete, the PIE vector table should be initialized by the user's code. Then the application enables the PIE vector table. From that point on the interrupt vectors are fetched from the PIE vector table.

  • Page 127: Interrupt Sources

    Interrupt Sources www.ti.com Interrupt Sources Figure 6-4 shows how the various interrupt sources are multiplexed within the devices. This multiplexing (MUX) scheme may not be exactly the same on all 28x devices. See the data manual of your particular device for details. Figure 6-4.

  • Page 128: Pie Interrupt Sources And External Interrupts (Xint3 - Xint7)

    Interrupt Sources www.ti.com Figure 6-5. PIE Interrupt Sources and External Interrupts (XINT3 – XINT7) XINT3 Interrupt Control Latch XINT3CR(15:0) GPIOXINT3SEL(4:0) XINT4 Interrupt Control Latch XINT4CR(15:0) GPIOXINT4SEL(4:0) INT1 XINT5 Latch Interrupt Control INT12 XINT5CR(15:0) Core GPIOXINT5SEL(4:0) XINT6 Interrupt Control Latch XINT6CR(15:0) GPIOXINT6SEL(4:0) GPIO32.int XINT7...

  • Page 129: 6.3.1 Procedure For Handling Multiplexed Interrupts

    Interrupt Sources www.ti.com 6.3.1 Procedure for Handling Multiplexed Interrupts The PIE module multiplexes eight peripheral and external pin interrupts into one CPU interrupt. These interrupts are divided into 12 groups: PIE group 1 - PIE group 12. Each group has an associated enable PIEIER and flag PIEIFR register.

  • Page 130: 6.3.2 Procedures For Enabling And Disabling Multiplexed Peripheral Interrupts

    Interrupt Sources www.ti.com 6.3.2 Procedures for Enabling And Disabling Multiplexed Peripheral Interrupts The proper procedure for enabling or disabling an interrupt is by using the peripheral interrupt enable/disable flags. The primary purpose of the PIEIER and CPU IER registers is for software prioritization of interrupts within the same PIE interrupt group.

  • Page 131: 6.3.3 Flow Of A Multiplexed Interrupt Request From A Peripheral To The Cpu

    Interrupt Sources www.ti.com 6.3.3 Flow of a Multiplexed Interrupt Request From a Peripheral to the CPU Figure 6-6 shows the flow with the steps shown in circled numbers. Following the diagram, the steps are described. Figure 6-6. Multiplexed Interrupt Request Flow Diagram interrupt enable interrupt...

  • Page 132: 6.3.4 The Pie Vector Table

    Interrupt Sources www.ti.com a. The vector for the highest priority interrupt within the group that is both enabled in the PIEIERx register, and flagged as pending in the PIEIFRx is fetched and used as the branch address. In this manner if an even higher priority enabled interrupt was flagged after Step 7, it will be serviced first.

  • Page 133: Pie Muxed Peripheral Interrupt Vector Table

    Interrupt Sources www.ti.com Table 6-4. PIE MUXed Peripheral Interrupt Vector Table INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 INT1.y WAKEINT TINT0 ADCINT XINT2 XINT1 Reserved SEQ2INT SEQ1INT (LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 (ADC) (ADC) 0xD4E 0xD4C 0xD4A...

  • Page 134: Pie Vector Table

    Interrupt Sources www.ti.com Table 6-4. PIE MUXed Peripheral Interrupt Vector Table (continued) INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0 Table 6-5. PIE Vector Table PIE Group Name VECTOR ID Address Size (x16) Description CPU Priority Priority...
  • Page 135 Interrupt Sources www.ti.com Table 6-5. PIE Vector Table (continued) PIE Group Name VECTOR ID Address Size (x16) Description CPU Priority Priority USER6 0x0000 0D32 User Defined Trap USER7 0x0000 0D34 User Defined Trap USER8 0x0000 0D36 User Defined Trap USER9 0x0000 0D38 User Defined Trap USER10...
  • Page 136 Interrupt Sources www.ti.com Table 6-5. PIE Vector Table (continued) PIE Group Name VECTOR ID Address Size (x16) Description CPU Priority Priority INT3.7 0x0000 0D6C Reserved INT3.8 0x0000 0D6E Reserved 8 (lowest) PIE Group 4 Vectors - MUXed into CPU INT4 INT4.1 0x0000 0D70 ECAP1_INT...
  • Page 137 Interrupt Sources www.ti.com Table 6-5. PIE Vector Table (continued) PIE Group Name VECTOR ID Address Size (x16) Description CPU Priority Priority INT7.4 0x0000 0DA6 DINTCH4 DMA Channel 4 INT7.5 0x0000 0DA8 DINTCH5 DMA Channel 5 INT7.6 0x0000 0DAA DINTCH6 DMA Channel 6 INT7.7 0x0000 0DAC Reserved...
  • Page 138 Interrupt Sources www.ti.com Table 6-5. PIE Vector Table (continued) PIE Group Name VECTOR ID Address Size (x16) Description CPU Priority Priority INT11.1 0x0000 0DE0 Reserved 1 (highest) INT11.2 0x0000 0DE2 Reserved INT11.3 0x0000 0DE4 Reserved INT11.4 0x0000 0DE6 Reserved INT11.5 0x0000 0DE8 Reserved INT11.6...

  • Page 139: Pie Configuration Registers

    PIE Configuration Registers www.ti.com PIE Configuration Registers The registers controlling the functionality of the PIE block are shown in Table 6-6. Table 6-6. PIE Configuration and Control Registers Name Address Size (x16) Description PIECTRL 0x0000 - 0CE0 PIE, Control Register PIEACK 0x0000 - 0CE1 PIE, Acknowledge Register...

  • Page 140: Pie Interrupt Registers

    PIE Interrupt Registers www.ti.com PIE Interrupt Registers Figure 6-7. PIECTRL Register (Address CE0) PIEVECT ENPIE R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-7. PIECTRL Register Address Field Descriptions Bits Field Value Description 15-1 PIEVECT These bits indicate the address within the PIE vector table from which the vector was fetched.

  • Page 141: 6.5.1 Pie Interrupt Flag Registers

    PIE Interrupt Registers www.ti.com 6.5.1 PIE Interrupt Flag Registers There are twelve PIEIFR registers, one for each CPU interrupt used by the PIE module (INT1-INT12). Figure 6-9. PIEIFRx Register (x = 1 to 12) Reserved INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1...

  • Page 142: Cpu Interrupt Flag Register (Ifr)

    PIE Interrupt Registers www.ti.com Table 6-10. PIEIERx Register (x = 1 to 12) Field Descriptions Bits Field Description 15-8 Reserved Reserved INTx.8 These register bits individually enable an interrupt within a group and behave very much like the core interrupt enable register.

  • Page 143: Interrupt Flag Register (Ifr) - Cpu Register

    PIE Interrupt Registers www.ti.com Figure 6-11. Interrupt Flag Register (IFR) — CPU Register RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0...

  • Page 144: Interrupt Enable Register (Ier) And Debug Interrupt Enable Register (Dbgier)

    PIE Interrupt Registers www.ti.com Table 6-11. Interrupt Flag Register (IFR) — CPU Register Field Descriptions (continued) Bits Field Value Description INT6 Interrupt 6 flag. INT6 is the flag for interrupts connected to CPU interrupt level INT6. No INT6 interrupt is pending At least one INT6 interrupt is pending.

  • Page 145: Interrupt Enable Register (Ier) - Cpu Register

    PIE Interrupt Registers www.ti.com Figure 6-12. Interrupt Enable Register (IER) — CPU Register RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0...

  • Page 146: Debug Interrupt Enable Register (Dbgier) - Cpu Register

    PIE Interrupt Registers www.ti.com Table 6-12. Interrupt Enable Register (IER) — CPU Register Field Descriptions (continued) Bits Field Value Description INT4 Interrupt 4 enable.INT4 enables or disables CPU interrupt level INT4. Level INT4 is disabled Level INT4 is enabled INT3 Interrupt 3 enable.INT3 enables or disables CPU interrupt level INT3.
  • Page 147 PIE Interrupt Registers www.ti.com Table 6-13. Debug Interrupt Enable Register (DBGIER) — CPU Register Field Descriptions (continued) Bits Field Value Description INT12 Interrupt 12 enable. INT12 enables or disables CPU interrupt level INT12. Level INT12 is disabled Level INT12 is enabled INT11 Interrupt 11 enable.

  • Page 148: External Interrupt Control Registers

    External Interrupt Control Registers www.ti.com External Interrupt Control Registers Seven external interrupts, XINT1 –XINT7 are supported. XINT13 is multiplexed with one non-maskable interrupt XNMI. Each of these external interrupts can be selected for negative or positive edge triggered and can also be enabled or disabled (including XNMI). The masked interrupts also contain a 16-bit free running up counter that is reset to zero when a valid interrupt edge is detected.

  • Page 149: External Interrupt 1 Counter (Xint1Ctr) (Address 7078H)

    External Interrupt Control Registers www.ti.com Table 6-15. External NMI Interrupt Control Register (XNMICR) Field Descriptions (continued) Bits Field Value Description Select Select the source for INT13 Timer 1 connected To INT13 XNMI_XINT13 connected To INT13 Enable This read/write bit enables or disables external interrupt NMI Disable XNMI interrupt Enable XNMI interrupt The XNMI Control Register (XNMICR) can be used to enable or disable the NMI interrupt to the CPU.

  • Page 150: External Nmi Interrupt Counter (Xnmictr) (Address 707Fh)

    External Interrupt Control Registers www.ti.com Table 6-18. External Interrupt 2 Counter (XINT2CTR) Field Descriptions Bits Field Description 15-0 INTCTR This is a free running 16-bit up-counter that is clocked at the SYSCLKOUT rate. The counter value is reset to 0x0000 when a valid interrupt edge is detected and then continues counting until the next valid interrupt edge is detected.

  • Page 151: Revision History

    Appendix A SPRUFB0C – September 2007 – Revised May 2009 Revision History Revision C of this document includes the changes shown in Table A-1. Table A-1. Changes Made in This Revision Location Additions, Deletions, Modifications Figure 3-7 Modified the OSC and PLL block diagram Section 2.1 Changed first para Section 1.2.3...
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