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3.6
HC Interrupt Disable Register (HCINTERRUPTDISABLE)
The HC interrupt disable register (HCINTERRUPTDISABLE) is used to clear bits in the HC interrupt
enable register (HCINTERRUPTENABLE). HCINTERRUPTDISABLE is shown in
in
Table
7.
31
30
29
MIE
OC
R/W-0
R-0
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions
Bit
Field
Value
31
MIE
0
1
30
OC
0-1
29-7
Reserved
0
6
RHSC
0
1
5
FNO
0
1
4
UE
0
1
3
RD
0
1
2
SF
0
1
1
WDH
0
1
0
SO
0
1
SPRUFM8 – June 2009
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Figure 7. HC Interrupt Disable Register (HCINTERRUPTDISABLE)
Reserved
R-0
Description
Master interrupt enable. Read always returns 0.
No effect.
Clears the MIE bit in the HC interrupt enable register (HCINTERRUPTENABLE).
Ownership change.
Reserved
Root hub status change. Read always returns 0.
No effect.
Clears the RHSC bit in the HC interrupt enable register (HCINTERRUPTENABLE).
Frame number overflow. Read always returns 0.
No effect.
Clears the FNO bit in the HC interrupt enable register (HCINTERRUPTENABLE).
Unrecoverable error. Read always returns 0.
No effect.
Clears the UE bit in the HC interrupt enable register (HCINTERRUPTENABLE).
Resume detected. Read always returns 0.
No effect.
Clears the RD bit in the HC interrupt enable register (HCINTERRUPTENABLE).
Start of frame. Read always returns 0.
No effect.
Clears the SF bit in the HC interrupt enable register (HCINTERRUPTENABLE).
Write done head. Read always returns 0.
No effect.
Clears the WDH bit in the HC interrupt enable register (HCINTERRUPTENABLE).
Scheduling overrun. Read always returns 0.
No effect.
Clears the SO bit in the HC interrupt enable register (HCINTERRUPTENABLE).
Reserved
R-0
7
6
5
4
RHSC
FNO
UE
R/W-0
R/W-0
R/W-0
Universal Serial Bus OHCI Host Controller
Registers
Figure 7
and described
16
3
2
1
0
RD
SF
WDH
SO
R/W-0
R/W-0
R/W-0
R/W-0
19
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