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Texas Instruments TMS320x281 series Reference Manual

Texas Instruments TMS320x281 series Reference Manual

Enhanced controller area network (ecan)
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TMS320x281x
Enhanced Controller Area Network (eCAN)
Reference Guide
Literature Number: SPRU074F
May 2002 – Revised January 2009

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  • Page 1 TMS320x281x Enhanced Controller Area Network (eCAN) Reference Guide Literature Number: SPRU074F May 2002 – Revised January 2009...
  • Page 2 SPRU074F – May 2002 – Revised January 2009 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Contents ..........................Preface ....................... Architecture ......................CAN Overview ......................1.1.1 Features ..................... 1.1.2 Block Diagram ............. 1.1.3 eCAN Compatibility With Other TI CAN Modules ................... The CAN Network and Module ..................1.2.1 CAN Protocol Overview ....................eCAN Controller Overview ................. 1.3.1 Standard CAN Controller (SCC) Mode .......................
  • Page 4 www.ti.com ....................2.18 Timer Management Unit ................... 2.18.1 Time Stamp Functions ....................2.18.2 Time-Out Functions ............2.18.3 Behavior/Usage of MTOF0/1 Bit in User Applications ......................2.19 Mailbox Layout ................. 2.19.1 Message Identifier Register (MSGID) .................... 2.19.2 CPU Mailbox Access ............... 2.19.3 Message-Control Register (MSGCTRL) .............

  • Page 5: List Of Figures

    www.ti.com List of Figures ................eCAN Block Diagram and Interface Circuit ......................CAN Data Frame ..................Architecture of the eCAN Module ..................... eCAN-A Memory Map ..................... eCAN-B Memory Map ..................Mailbox-Enable Register (CANME) ..................Mailbox-Direction Register (CANMD) ............... Transmission-Request Set Register (CANTRS) ..............
  • Page 6 www.ti.com List of Tables ........................ Register Map .................... eCAN-A Mailbox RAM Layout ......... Addresses of LAM, MOTS and MOTO registers for mailboxes (eCAN-A) .................... eCAN-B Mailbox Ram Layout ........Addresses of LAM, MOTS, and MOTO Registers for Mailboxes (eCAN-B) ................Message Object Behavior Configuration ..............

  • Page 7: Preface

    • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments The following documents describe the x281x device and related peripherals. Copies of these documents are available for downloading at www.ti.com.
  • Page 8 Related Documentation From Texas Instruments www.ti.com SPRU059— TMS320x28xx, 28xxx Serial Peripheral Interface (SPI) Reference Guide describes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate.

  • Page 9: Architecture

    Chapter 1 SPRU074F – May 2002 – Revised January 2009 Architecture The enhanced Controller Area Network (eCAN) module implemented in the C28x™ DSP is a full-CAN controller and is compatible with the CAN 2.0B standard (active). It uses established protocol to communicate serially with other controllers in electrically noisy environments.

  • Page 10: Can Overview

    CAN Overview www.ti.com CAN Overview Figure 1–1 shows the major blocks of the eCAN and the interface circuits. 1.1.1 Features The eCAN module has the following features: • Fully compliant with CAN protocol, version 2.0B • Supports data rates up to 1 Mbps •...

  • Page 11: Block Diagram

    The eCAN module is identical to the “High-end CAN Controller (HECC)” used in the TMS470™ series microcontrollers from Texas Instruments with some minor changes. The eCAN module features several enhancements (such as increased number of mailboxes with individual acceptance masks, time stamping, etc.) over the CAN module featured in 240x™...

  • Page 12: The Can Network And Module

    The CAN Network and Module www.ti.com The CAN Network and Module The controller area network (CAN) uses a serial multimaster communication protocol that efficiently supports distributed real-time control, with a very high level of security, and a communication rate of up to 1 Mbps.

  • Page 13: Ecan Controller Overview

    eCAN Controller Overview www.ti.com Figure 1-3. Architecture of the eCAN Module CAN controller Message Controller Transmit Buffer Receive Buffer CAN Protocol Kernel (CPK) CAN Transceiver CAN Bus The receive and transmit buffers are transparent to the user and are not accessible by user code. Two functions of the CPK are to decode all messages received on the CAN bus according to the CAN protocol and to transfer these messages into a receive buffer.

  • Page 14: Standard Can Controller (Scc) Mode

    eCAN Controller Overview www.ti.com When a message must be transmitted, the message controller transfers the message into the transmit buffer of the CPK in order to start the message transmission at the next bus-idle state. When more than one message must be transmitted, the message with the highest priority that is ready to be transmitted is transferred into the CPK by the message controller.

  • Page 15: Memory Map

    eCAN Controller Overview www.ti.com 1.3.2 Memory Map The eCAN module has two different address segments mapped in the memory. The first segment is used to access the control registers, the status registers, the acceptance masks, the time stamp, and the time-out of the message objects.

  • Page 16: Ecan-A Memory Map

    eCAN Controller Overview www.ti.com Figure 1-4. eCAN-A Memory Map eCAN−A Control and Status Registers Mailbox Enable − CANME Mailbox Direction − CANMD Transmission Request Set − CANTRS Transmission Request Reset − CANTRR Transmission Acknowledge − CANTA eCAN−A Registers (512 Bytes) Abort Acknowledge −...

  • Page 17: Ecan-B Memory Map

    eCAN Controller Overview www.ti.com Figure 1-5. eCAN-B Memory Map eCAN−B Control and Status Registers Mailbox Enable − CANME Mailbox Direction − CANMD Transmission Request Set − CANTRS Transmission Request Reset − CANTRR Transmission Acknowledge − CANTA eCAN−B Memory (512 Bytes) Abort Acknowledge −...

  • Page 18: Ecan Control And Status Registers

    eCAN Controller Overview www.ti.com 1.3.3 eCAN Control and Status Registers The eCAN registers listed in Table 1-1 are used by the CPU to configure and control the CAN controller and the message objects. Table 1-1. Register Map REGISTER NAME ECAN-A ECAN-B SIZE DESCRIPTION...

  • Page 19: Message Objects

    Message Objects www.ti.com Message Objects The eCAN module has 32 different message objects (mailboxes). Each message object can be configured to either transmit or receive. Each message object has its individual acceptance mask. A message object consists of a message mailbox with: •...

  • Page 20: Ecan-A Mailbox Ram Layout

    Message Mailbox www.ti.com Table 1-2. eCAN-A Mailbox RAM Layout Mailbox MSGID MSGCTRL CANMDL CANMDH MSGIDL-MSGIDH MSGCTRL-Rsvd CANMDL_L- CANMDL_H CANMDH_L- CANMDH_H 6100-6101h 6102-6103h 6104-6105h 6106-6107h 6108-6109h 610A-610Bh 610C-610Dh 610E-610Fh 6110 - 6111h 6112-6113h 6114-6115h 6116-6117h 6118-6119h 611A-611Bh 611C-611Dh 611E-611Fh 6120-6121h 6122-6123h 6124-6125h 6126-6127h 6128-6129h...

  • Page 21: Addresses Of Lam, Mots And Moto Registers For Mailboxes (Ecan-A)

    Message Mailbox www.ti.com Table 1-3. Addresses of LAM, MOTS and MOTO registers for mailboxes (eCAN-A) Mailbox MOTS MOT0 6040h-6041h 6080h-6081h 60C0h-60C1h 6042h-6043h 6082h-6083h 60C2h-60C3h 6044h-6045h 6084h-6085h 60C4h-60C5h 6046h-6047h 6086h-6087h 60C6h-60C7h 6048h-6049h 6088h-6089h 60C8h-60C9h 604Ah-604Bh 608Ah-608Bh 60CAh-60CBh 604Ch-604Dh 608Ch-608Dh 60CCh-60CDh 604Eh-604Fh 608Eh-608Fh 60CEh-60CFh 6050h-6051h...

  • Page 22: Ecan-B Mailbox Ram Layout

    Message Mailbox www.ti.com Table 1-4. eCAN-B Mailbox Ram Layout MSGID MSGCTRL CANMDL CANMDH MSGIDL-MSGIDH MSGCTRL - Rsvd CANMDL_L - CANMDL_H CANMDH_L - CANMDH_H 6300-6301h 6302-6303h 6304-6305h 6306-6307h 6308-6309h 630A-630Bh 630C-630Dh 630E-630Fh 6310-6311h 6312-6313h 6314-6315h 6316-6317h 6318-6319h 631A-631Bh 631C-631Dh 631E-631Fh 6320-6321h 6322-6323h 6324-6325h 6326-6327h...

  • Page 23: Transmit Mailbox

    Message Mailbox www.ti.com Table 1-5. Addresses of LAM, MOTS, and MOTO Registers for Mailboxes (eCAN-B) Mailbox MOTS MOT0 6240h–6241h 6280h–6281h 62C0h–62C1h 6242h– 6243h 6282h–6283h 62C2h–62C3h 6244h– 6245h 6284h–6285h 62C4h–62C5h 6246h–6247h 6286h–6287h 62C6h–62C7h 6248h–6249h 6288h–6289h 62C8h–62C9h 624Ah–624Bh 628Ah–628Bh 62CAh–62CBh 624Ch–624Dh 628Ch–628Dh 62CCh–62CDh 624Eh–624Fh 628Eh–628Fh...

  • Page 24: Receive Mailbox

    Message Mailbox www.ti.com If more than one mailbox is configured as transmit mailbox and more than one corresponding TRS[n] is set, the messages are sent one after another in falling order beginning with the mailbox with the highest priority. In the SCC-compatibility mode, the priority of the mailbox transmission depends on the mailbox number. The highest mailbox number (=15) comprises the highest transmit priority.

  • Page 25: Ecan Registers

    Chapter 2 SPRU074F – May 2002 – Revised January 2009 eCAN Registers This chapter contains the registers and bit descriptions....................Topic Page ..........Mailbox Enable Register (CANME) ........... Mailbox-Direction Register (CANMD) ......Transmission-Request Set Register (CANTRS) ......Transmission-Request-Reset Register (CANTRR) ......

  • Page 26: Mailbox Enable Register (Canme)

    Mailbox Enable Register (CANME) www.ti.com Mailbox Enable Register (CANME) This register is used to enable/disable individual mailboxes. Figure 2-1. Mailbox-Enable Register (CANME) CANME[31:0] R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 2-1. Mailbox-Enable Register (CANME) Field Descriptions Field Value Description...

  • Page 27: Mailbox-Direction Register (Canmd)

    Mailbox-Direction Register (CANMD) www.ti.com Mailbox-Direction Register (CANMD) This register is used to configure a mailbox for transmit or receive operation. Figure 2-2. Mailbox-Direction Register (CANMD) CANMD[31:0] R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 2-2. Mailbox-Direction Register (CANMD) Field Descriptions Field Value Description...

  • Page 28: Transmission-Request Set Register (Cantrs)

    Transmission-Request Set Register (CANTRS) www.ti.com Transmission-Request Set Register (CANTRS) When mailbox n is ready to be transmitted, the CPU should set the TRS[n] bit to 1 to start the transmission. These bits are normally set by the CPU and cleared by the CAN module logic. The CAN module can set these bits for a remote frame request.

  • Page 29: Transmission-Request-Reset Register (Cantrr)

    Transmission-Request-Reset Register (CANTRR) www.ti.com Transmission-Request-Reset Register (CANTRR) These bits can only be set by the CPU and reset by the internal logic. These bits are reset when a transmission is successful or is aborted. If the CPU tries to set a bit while the CAN tries to clear it, the bit is set.

  • Page 30: Transmission-Acknowledge Register (Canta)

    Transmission-Acknowledge Register (CANTA) www.ti.com Transmission-Acknowledge Register (CANTA) If the message of mailbox n was sent successfully, the bit TA[n] is set. This also sets the GMIF0/GMIF1 (GIF0.15/GIF1.15) bit if the corresponding interrupt mask bit in the CANMIM register is set. The GMIF0/GMIF1 bit initiates an interrupt.

  • Page 31: Abort-Acknowledge Register (Canaa)

    Abort-Acknowledge Register (CANAA) www.ti.com Abort-Acknowledge Register (CANAA) If the transmission of the message in mailbox n was aborted, the bit AA[n] is set and the AAIF (GIF.14) bit is set, which may generate an interrupt if enabled. The bits in CANAA are reset by writing a 1 from the CPU. Writing a 0 has no effect. If the CPU tries to reset a bit and the CAN tries to set the bit at the same time, the bit is set.

  • Page 32: Received-Message-Pending Register (Canrmp)

    Received-Message-Pending Register (CANRMP) www.ti.com Received-Message-Pending Register (CANRMP) If mailbox n contains a received message, the bit RMP[n] of this register is set. These bits can be reset only by the CPU and set by the internal logic. A new incoming message overwrites the stored one if the OPC[n](OPC.31-0) bit is cleared, otherwise the next mailboxes are checked for a matching ID.

  • Page 33: Received-Message-Lost Register (Canrml)

    Received-Message-Lost Register (CANRML) www.ti.com Received-Message-Lost Register (CANRML) An RML[n] bit is set if an old message has been overwritten by a new one in mailbox n. These bits can only be reset by the CPU, and set by the internal logic. The bits can be cleared by a write access to the CANRMP register with a 1 at the corresponding bit location.

  • Page 34: Remote-Frame-Pending Register (Canrfp)

    Remote-Frame-Pending Register (CANRFP) www.ti.com Remote-Frame-Pending Register (CANRFP) Whenever a remote frame request is received by the CAN module, the corresponding bit RFP[n] in the remote frame pending register is set. If a remote frame is stored in a receive mailbox (AAM=0, CANMD=1), the RFPn bit will not be set.
  • Page 35 Remote-Frame-Pending Register (CANRFP) www.ti.com The behavior of the message object n is configured with CANMD[n] (CANMD.31-0), the AAM (MSGID.29), and RTR (MSGCTRL.4). It shows how to configure a message object according to the desired behavior. To summarize, a message object can be configured with four different behaviors: 1.

  • Page 36: Global Acceptance Mask Register (Cangam)

    Global Acceptance Mask Register (CANGAM) www.ti.com 2.10 Global Acceptance Mask Register (CANGAM) The global-acceptance mask is used by the eCAN in SCC mode. The global-acceptance mask is used for the mailboxes 6 to 15 if the AME bit (MSGID.30) of the corresponding mailbox is set. A received message is only stored in the first mailbox with a matching identifier.

  • Page 37: Master Control Register (Canmc)

    Master Control Register (CANMC) www.ti.com 2.11 Master Control Register (CANMC) This register is used to control the settings of the CAN module. Some bits of the CANMC register are EALLOW protected. For read/write operations, only 32-bit access is supported. Figure 2-11. Master Control Register (CANMC) Reserved SUSP R/W-0...
  • Page 38 Master Control Register (CANMC) www.ti.com Table 2-11. Master Control Register (CANMC) Field Descriptions (continued) Field Value Description Power down mode request. This bit is automatically cleared by the eCAN module upon wakeup from low-power mode. This bit is EALLOW protected. The local power-down mode is requested.

  • Page 39: Can Module Action In Suspend

    Master Control Register (CANMC) www.ti.com 2.11.1 CAN Module Action in SUSPEND 1. If there is no traffic on the CAN bus and SUSPEND mode is requested, the node goes into SUSPEND mode. 2. If there is traffic on the CAN bus and SUSPEND mode is requested, the node goes into SUSPEND mode when the ongoing frame is over.

  • Page 40: Bit-Timing Configuration Register (Canbtc)

    Bit-Timing Configuration Register (CANBTC) www.ti.com 2.12 Bit-Timing Configuration Register (CANBTC) The CANBTC register is used to configure the CAN node with the appropriate network-timing parameters. This register must be programmed before using the CAN module. This register is write-protected in user mode and can only be written in initialization mode (see Section 3.6.1).
  • Page 41 Bit-Timing Configuration Register (CANBTC) www.ti.com Field Value Description This parameter sets the number of samples used by the CAN module to determine the actual level of the CAN bus. When the SAM bit is set, the level determined by the CAN bus corresponds to the result from the majority decision of the last three values.

  • Page 42: Error And Status Register (Canes)

    Error and Status Register (CANES) www.ti.com 2.13 Error and Status Register (CANES) The status of the CAN module is shown by the Error and Status Register (CANES) and the error counter registers, which are described in this section. The error and status register comprises information about the actual status of the CAN module and displays bus error flags as well as error status flags.
  • Page 43 Error and Status Register (CANES) www.ti.com Table 2-13. Error and Status Register (CANES) Field Descriptions (continued) Field Value Description Error-passive state The CAN module is in error-passive mode. CANTEC has reached 128. The CAN module is in error-active mode. Warning status One of the two error counters (CANREC or CANTEC) has reached the warning level of 96.

  • Page 44: Can Error Counter Registers (Cantec/Canrec)

    CAN Error Counter Registers (CANTEC/CANREC) www.ti.com 2.14 CAN Error Counter Registers (CANTEC/CANREC) The CAN module contains two error counters: the receive error counter (CANREC) and the transmit error counter (CANTEC). The values of both counters can be read via the CPU interface. These counters are incremented or decremented according to the CAN protocol specification version 2.0.

  • Page 45: Interrupt Registers

    Interrupt Registers www.ti.com 2.15 Interrupt Registers Interrupts are controlled by the interrupt flag registers, interrupt mask registers and mailbox interrupt level registers. These registers are described in the following subsections. 2.15.1 Global Interrupt Flag Registers (CANGIF0/CANGIF1) These registers allow the CPU to identify the interrupt source. The interrupt flag bits are set if the corresponding interrupt condition did occur.

  • Page 46: Global Interrupt Flag 0 Register (Cangif0)

    Interrupt Registers www.ti.com Figure 2-16. Global Interrupt Flag 0 Register (CANGIF0) Reserved Reserved MTOF0 TCOF0 RC-0 GMIF0 AAIF0 WDIF0 WUIF0 RMLIF0 BOIF0 EPIF0 WLIF0 R/W-0 RC-0 RC-0 RC-0 RC-0 RC-0 Reserved MIV0.4 MIV0.3 MIV0.2 MIV0.1 MIV0.0 R/W-0 LEGEND: R/W = Read/Write; R = Read; C = Clear; -n = value after reset Figure 2-17.

  • Page 47: Global Interrupt Flag Registers (Cangif0/Cangif1) Field Descriptions

    Interrupt Registers www.ti.com Table 2-14. Global Interrupt Flag Registers (CANGIF0/CANGIF1) Field Descriptions Field Value Description 31:18 Reserved Reserved. Reads are undefined and writes have no effect. MTOF0/1 Mailbox time-out flag. This bit is not available in the SCC mode. One of the mailboxes did not transmit or receive a message within the specified time frame. No time out for the mailboxes occurred.

  • Page 48: Global Interrupt Mask Register (Cangim)

    Interrupt Registers www.ti.com 2.15.2 Global Interrupt Mask Register (CANGIM) The set up for the interrupt mask register is the same as for the interrupt flag register. If a bit is set, the corresponding interrupt is enabled. This register is EALLOW protected. Figure 2-18.
  • Page 49 Interrupt Registers www.ti.com Table 2-15. Global Interrupt Mask Register (CANGIM) Field Descriptions (continued) Field Value Description WLIM Warning level interrupt mask Enabled Disabled Reserved Reads are undefined and writes have no effect. Global interrupt level for the interrupts TCOF, WDIF, WUIF, BOIF, EPIF, RMLIF, AAIF and WLIF. All global interrupts are mapped to the ECAN1INT interrupt line.

  • Page 50: Mailbox Interrupt Mask Register (Canmim)

    Interrupt Registers www.ti.com 2.15.3 Mailbox Interrupt Mask Register (CANMIM) There is one interrupt flag available for each mailbox. This can be a receive or a transmit interrupt depending on the configuration of the mailbox. This register is EALLOW protected. Figure 2-19. Mailbox Interrupt Mask Register (CANMIM) MIM.31:0 R/W-0 LEGEND: R/W = Read/Write;...

  • Page 51: Mailbox Interrupt Level Register (Canmil)

    Interrupt Registers www.ti.com 2.15.4 Mailbox Interrupt Level Register (CANMIL) Each of the 32 mailboxes may initiate an interrupt on one of the two interrupt lines. Depending on the setting in the mailbox interrupt level register (CANMIL), the interrupt is generated on ECAN0INT (MILn = 0) or on line ECAN1INT (MIL[n] = 1).

  • Page 52: Overwrite Protection Control Register (Canopc)

    Overwrite Protection Control Register (CANOPC) www.ti.com 2.16 Overwrite Protection Control Register (CANOPC) If there is an overflow condition for mailbox n (RMP[n] is set to 1 and a new receive message would fit for mailbox n), the new message is stored depending on the settings in the CANOPC register. If the corresponding bit OPC[n] is set to 1, the old message is protected against being overwritten by the new message;...

  • Page 53: Ecan I/O Control Registers (Cantioc, Canrioc)

    eCAN I/O Control Registers (CANTIOC, CANRIOC) www.ti.com 2.17 eCAN I/O Control Registers (CANTIOC, CANRIOC) The CANTX and CANRX pins should be configured for CAN use. This is done using the CANTIOC and CANRIOC registers. Figure 2-22. TX I/O Control Register (CANTIOC) Reserved Reserved TXFU...

  • Page 54: Rx I/O Control Register (Canrioc)

    eCAN I/O Control Registers (CANTIOC, CANRIOC) www.ti.com Figure 2-23. RX I/O Control Register (CANRIOC) Reserved Reserved RXFU Reserved RWP- LEGEND: RWP = Read in all modes, write in EALLOW-mode only; R = Read only; -n = value after reset; x = indeterminate Table 2-20.

  • Page 55: Timer Management Unit

    Timer Management Unit www.ti.com 2.18 Timer Management Unit Several functions are implemented in the eCAN to monitor the time when messages are transmitted/received. A separate state machine is included in the eCAN to handle the time-control functions. This state machine has lower priority when accessing the registers than the CAN state machine has.

  • Page 56: Time-Stamp Counter Register (Cantsc)

    Timer Management Unit www.ti.com 2.18.1.1 Time-Stamp Counter Register (CANTSC) This register holds the time-stamp counter value at any instant of time. This is a free-running 32-bit timer which is clocked by the bit clock of the CAN bus. For example, at a bit rate of 1 Mbps, CANTSC would increment every 1 µs.

  • Page 57: Message Object Time Stamp Registers (Mots)

    Timer Management Unit www.ti.com 2.18.1.2 Message Object Time Stamp Registers (MOTS) This register holds the value of the TSC when the corresponding mailbox data was successfully transmitted or received. Each mailbox has its own MOTS register. Figure 2-25. Message Object Time Stamp Registers (MOTS) MOTS31:0 R/W-x LEGEND: R/W = Read/Write;...

  • Page 58: Time-Out Functions

    Timer Management Unit www.ti.com 2.18.2 Time-Out Functions To ensure that all messages are sent or received within a predefined period, each mailbox has its own time-out register. If a message has not been sent or received by the time indicated in the time-out register and the corresponding bit TOC[n] is set in the TOC register, a flag is set in the time-out status register (TOS).

  • Page 59: Time-Out Control Register (Cantoc)

    Timer Management Unit www.ti.com 2.18.2.2 Time-Out Control Register (CANTOC) This register controls whether or not time-out functionality is enabled for a given mailbox. Figure 2-27. Time-Out Control Register (CANTOC) TOC31:0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 2-24.

  • Page 60: Behavior/Usage Of Mtof0/1 Bit In User Applications

    Timer Management Unit www.ti.com 2.18.2.3 Time-Out Status Register (CANTOS) This register holds the status information of mailboxes that have timed out. Figure 2-28. Time-Out Status Register (CANTOS) TOS31:0 R/C-0 LEGEND: R/C = Read/Clear; -n = value after reset Table 2-25. Time-Out Status Register (CANTOS) Field Descriptions Field Value Description...

  • Page 61: Mailbox Layout

    Mailbox Layout www.ti.com 2.19 Mailbox Layout The following four 32-bit registers comprise each mailbox: • MSGID – Stores the message ID • MSGCTRL – Defines number of bytes, transmission priority and remote frames • CANMDL – 4 bytes of data •...

  • Page 62: Cpu Mailbox Access

    Mailbox Layout www.ti.com Table 2-26. Message Identifier Register (MSGID) Field Descriptions (continued) Field Value Description 28:0 ID[28:0] Message identifier In standard identifier mode, if the IDE bit (MSGID.31) = 0, the message identifier is stored in bits ID.28:18. In this case, bits ID.17:0 have no meaning. In extended identifier mode, if the IDE bit (MSGID.31) = 1, the message identifier is stored in bits ID.28:0.

  • Page 63: Message-Control Register (Msgctrl)

    Mailbox Layout www.ti.com 2.19.3 Message-Control Register (MSGCTRL) For a transmit mailbox, this register specifies the number of bytes to be transmitted and the transmission priority. It also specifies the remote-frame operation. Note: As part of the CAN module initialization process, all the bits of the MSGCTRLn registers must first be initialized to zero before proceeding to initialize the various bit fields to the desired values.

  • Page 64: Message Data Registers (Canmdl, Canmdh)

    Mailbox Layout www.ti.com 2.19.4 Message Data Registers (CANMDL, CANMDH) Eight bytes of the mailbox are used to store the data field of a CAN message. The setting of DBO (MC.10) determines the ordering of stored data. The data is transmitted or received from the CAN bus, starting with byte 0.

  • Page 65: Acceptance Filter

    Acceptance Filter www.ti.com 2.20 Acceptance Filter The identifier of the incoming message is first compared to the message identifier of the mailbox (which is stored in the mailbox). Then, the appropriate acceptance mask is used to mask out the bits of the identifier that should not be compared.

  • Page 66: Local-Acceptance-Mask Register (Lamn)

    Acceptance Filter www.ti.com Figure 2-35. Local-Acceptance-Mask Register (LAMn) LAMI Reserved LAMn[28:16] R/W-0 R/W-0 R/W-0 LAMn[15:0] R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 2-28. Local-Acceptance-Mask Register (LAMn) Field Descriptions Field Value Description LAMI Local-acceptance-mask identifier extension bit Standard and extended frames can be received.

  • Page 67: Ecan Configuration

    Chapter 3 SPRU074F – May 2002 – Revised January 2009 eCAN Configuration This section explains the process of initialization and describes the procedures to configure the eCAN module....................Topic Page ............CAN Module Initialization ............Steps to Configure eCAN .........

  • Page 68: Can Module Initialization

    CAN Module Initialization www.ti.com CAN Module Initialization The CAN module must be initialized before the utilization. Initialization is only possible if the module is in initialization mode. Figure 3-1 is a flow chart showing the process. Programming CCR (CANMC.12) = 1 sets the initialization mode. The initialization can be performed only when CCE (CANES.4) = 1.

  • Page 69: Can Bit-Timing Configuration

    CAN Module Initialization www.ti.com 3.1.1 CAN Bit-Timing Configuration The CAN protocol specification partitions the nominal bit time into four different time segments: SYNC_SEG: This part of bit time is used to synchronize the various nodes on the bus. An edge is expected to lie within this segment.

  • Page 70: Bit Configuration Parameters For 150-Mhz Can Clock

    CAN Module Initialization www.ti.com Where bit-time is the number of time quanta (TQ) per bit. SYSCLKOUT is the CAN module system clock frequency, which is the same as the CPU clock frequency. BRP is the value of BRP (CANBTC.23-16). Bit-time is defined as follows: Bit-time = (TSEG1 + 1) + (TSEG2 + 1) + 1...

  • Page 71: Bit Configuration Parameters For 100-Mhz Can Clock

    CAN Module Initialization www.ti.com 3.1.4 Bit Configuration Parameters for 100-MHz CAN Clock Table 3-4 shows how the BRP field may be changed to achieve different bit rates with a BT of 10 for an 80% SP. Table 3-4. BRP Field for Bit Rates (BT = 10, TSEG1 = 6, TSEG2 = 1, Sampling Point = 80%) CAN Bus Speed...

  • Page 72: Eallow Protection

    Steps to Configure eCAN www.ti.com 3.1.5 EALLOW Protection To protect against inadvertent modification, some critical registers/bits of the eCAN module are EALLOW protected. These registers/bits can be changed only if the EALLOW protection has been disabled. Following are the registers/ bits that are EALLOW protected in the eCAN module: •...

  • Page 73: Configuring A Mailbox For Transmit

    Steps to Configure eCAN www.ti.com 3.2.1 Configuring a Mailbox for Transmit To transmit a message, the following steps need to be performed (in this example, for mailbox 1): 1. Clear the appropriate bit in the CANTRS register to 0: Clear CANTRS.1 = 0 (Writing a 0 to TRS has no effect; instead, set TRR.1 and wait until TRS.1 clears.) If the RTR bit is set, the TRS bit can send a remote frame.

  • Page 74: Receiving A Message

    Handling of Remote Frame Mailboxes www.ti.com 4. Configure the mailbox as a receive mailbox by setting the corresponding flag in the mailbox direction register (CANMD.3 = 1). Make sure no other bits in this register are affected by this operation. 5.

  • Page 75: Answering A Remote Request

    Interrupts www.ti.com 3. Set the CANTRS flag for that mailbox. Since the mailbox is configured as receive, it only sends a remote request message to the other node. Set CANTRS.3 = 1 4. The module stores the answer in that mailbox and sets the RMP bit when it is received. This action can initiate an interrupt.

  • Page 76: Interrupts Scheme

    Interrupts www.ti.com – Bus-off interrupt: the CAN module enters the bus-off state – Error-passive interrupt: the CAN module enters the error-passive mode – Warning level interrupt: one or both error counters are greater than or equal to 96 – Time-stamp counter overflow interrupt (eCAN only): the time-stamp counter had an overflow Figure 3-3.

  • Page 77: Interrupts Scheme

    Interrupts www.ti.com 3.4.1 Interrupts Scheme The interrupt flags are set if the corresponding interrupt condition occurred. The system interrupt flags are set depending on the setting of GIL (CANGIM.2). If set, the global interrupts set the bits in the CANGIF1 register, otherwise they set in the CANGIF0 register.

  • Page 78: Interrupt Handling

    Interrupts www.ti.com 3.4.3 Interrupt Handling The CPU is interrupted by asserting one of the two interrupt lines. After handling the interrupt, which should generally also clear the interrupt source, the interrupt flag must be cleared by the CPU. To do this, the interrupt flag must be cleared in the CANGIF0 or CANGIF1 register.
  • Page 79 Interrupts www.ti.com This configuration puts all mailbox interrupts on line 1 and all system interrupts on line 0. Thus, the CPU can handle all system interrupts (which are always serious) with high priority, and the mailbox interrupts (on the other line) with a lower priority. All messages with a high priority can also be directed to the interrupt line 0.

  • Page 80: Can Power-Down Mode

    CAN Power-Down Mode www.ti.com 2. The PIEACK bit corresponding corresponding to the CAN module must be written with a 1, which can be accomplished with the following C language statement: PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU 3.

  • Page 81: Enabling/Disabling Clock To The Can Module

    CAN Power-Down Mode www.ti.com 2. The CAN module has signaled to the CPU that it is ready to enter LPM. In other words, device low-power modes should be entered into only after putting the CAN module in local power-down mode. 3.5.3 Enabling/Disabling Clock to the CAN Module The CAN module cannot be used unless the clock to the module is enabled.
  • Page 82 eCAN Configuration SPRU074F – May 2002 – Revised January 2009 Submit Documentation Feedback...

  • Page 83: Revision History

    Appendix A SPRU074F – May 2002 – Revised January 2009 Revision History This document was revised to SPRU074F from SPRU074E. The scope of the revisions was limited to technical changes as described in Table A-1. This appendix lists only revisions made in the most recent version.
  • Page 84 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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