Texas Instruments TMS320C28 series Reference Manual
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Texas Instruments TMS320C28 series Reference Manual

Texas Instruments TMS320C28 series Reference Manual

Floating point unit and instruction set
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TMS320C28x Floating Point Unit and
Instruction Set
Reference Guide
Literature Number: SPRUEO2A
June 2007 – Revised August 2008

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Summary of Contents for Texas Instruments TMS320C28 series

  • Page 1 TMS320C28x Floating Point Unit and Instruction Set Reference Guide Literature Number: SPRUEO2A June 2007 – Revised August 2008...
  • Page 2 SPRUEO2A – June 2007 – Revised August 2008 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Contents ..........................Preface ....................... Introduction ..............Introduction to the Central Processing Unit (CPU) ................Compatibility with the C28x Fixed-Point CPU ................1.2.1 Floating-Point Code Development ..............Components of the C28x plus Floating-Point CPU ....................1.3.1 Emulation Logic ....................... 1.3.2 Memory Map ..................
  • Page 4 www.ti.com List of Figures .................... FPU Functional Block Diagram ..................C28x With Floating-Point Registers ................Floating-point Unit Status Register (STF) ....................Repeat Block Register (RB) ........................ FPU Pipeline List of Tables ..............28x Plus Floating-Point CPU Register Summary ............Floating-point Unit Status (STF) Register Field Descriptions ................

  • Page 5: Preface

    Preface SPRUEO2A – June 2007 – Revised August 2008 Read This First This document describes the CPU architecture, pipeline, instruction set, and interrupts of the C28x floating-point DSP. About This Manual The TMS320C2000™ digital signal processor (DSP) platform is part of the TMS320™ DSP family. Notational Conventions This document uses the following conventions.
  • Page 6 Related Documentation www.ti.com SPRU949— TMS320x2833x, 2823x External Interface (XINTF) User's Guide describes the XINTF, which is a nonmultiplexed asynchronous bus, as it is used on the 2833x devices. SPRU963— TMS320x2833x, TMS320x2823x Boot ROM User's Guide describes the purpose and features of the bootloader (factory-programmed boot-loading software) and provides examples of code.

  • Page 7: Introduction

    Chapter 1 SPRUEO2A – June 2007 – Revised August 2008 Introduction The TMS320C2000™ DSP family consists of fixed-point and floating-point digital signal controllers (DSCs). TMS320C2000™ Digital Signal Controllers combine control peripheral integration and ease of use of a microcontroller (MCU) with the processing power and C efficiency of TI’s leading DSP technology.

  • Page 8: Introduction To The Central Processing Unit (Cpu)

    Introduction to the Central Processing Unit (CPU) www.ti.com Introduction to the Central Processing Unit (CPU) The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by adding registers and instructions to support IEEE single-precision floating point operations. This device draws from the best features of digital signal processing;...

  • Page 9: 1.2.1 Floating-Point Code Development

    Components of the C28x plus Floating-Point CPU www.ti.com 1.2.1 Floating-Point Code Development When developing C28x floating-point code use Code Composer Studio 3.3, or later, with at least service release 8. The C28x compiler V5.0, or later, is also required to generate C28x native floating-point opcodes.

  • Page 10: 1.3.1 Emulation Logic

    Memory Interface www.ti.com 1.3.1 Emulation Logic The emulation logic is identical to that on the C28x fixed-point CPU. This logic includes the following features. For more details about these features, refer to the TMS320C28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430: •...

  • Page 11: 1.4.1 Address And Data Buses

    Memory Interface www.ti.com 1.4.1 Address and Data Buses Like the C28x, the memory interface has three address buses: • PAB: Program address bus The PAB carries addresses for reads and writes from program space. PAB is a 22-bit bus. • DRAB: Data-read address bus The 32-bit DRAB carries addresses for reads from data space.
  • Page 12 Introduction SPRUEO2A – June 2007 – Revised August 2008 Submit Documentation Feedback...

  • Page 13: Cpu Register Set

    Chapter 2 SPRUEO2A – June 2007 – Revised August 2008 CPU Register Set The C28x+FPU architecture is the same as the C28x CPU with an extended register and instruction set to support IEEE single-precision floating point operations. This section describes the extensions to the C28x architecture.

  • Page 14: Cpu Registers

    CPU Registers www.ti.com CPU Registers Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit registers. The additional floating-point unit registers are the following: • Eight floating-point result registers, RnH (where n = 0 - 7) •...
  • Page 15 CPU Registers www.ti.com Table 2-1. 28x Plus Floating-Point CPU Register Summary Register C28x C28x+FPU Size Description Value After Reset 32 bits Accumulator 0x00000000 16 bits High half of ACC 0x0000 16 bits Low half of ACC 0x0000 XAR0 16 bits Auxiliary register 0 0x00000000 XAR1...

  • Page 16: Floating-Point Status Register (Stf)

    CPU Registers www.ti.com 2.1.1 Floating-Point Status Register (STF) The floating-point status register (STF) reflects the results of floating-point operations. There are three basic rules for floating point operation flags: 1. Zero and negative flags are set based on moves to registers. 2.
  • Page 17 CPU Registers www.ti.com Table 2-2. Floating-point Unit Status (STF) Register Field Descriptions (continued) Bits Field Value Description Test Flag The TESTTF instruction can modify this flag based on the condition tested. The SETFLG and SAVE instructions can also be used to modify this flag. The condition tested with the TESTTF instruction is false.

  • Page 18: Repeat Block Register (Rb)

    CPU Registers www.ti.com 2.1.2 Repeat Block Register (RB) The repeat block instruction (RPTB) is a new instruction for C28x+FPU. This instruction allows you to repeat a block of code as shown in Example 2-2. Example 2-2. The Repeat Block (RPTB) Instruction uses the RB Register ;...
  • Page 19 CPU Registers www.ti.com Table 2-3. Repeat Block (RB) Register Field Descriptions (continued) Bits Field Value Description 22-16 Repeat Block End Address This 7-bit value specifies the end address location of the repeat block. The RE value is calculated by hardware based on the RSIZE field and the PC value when the RPTB instruction is executed. RE = lower 7 bits of (PC + 1 + RSIZE) 15-0 Repeat Count...
  • Page 20 CPU Register Set SPRUEO2A – June 2007 – Revised August 2008 Submit Documentation Feedback...

  • Page 21: Pipeline

    Chapter 3 SPRUEO2A – June 2007 – Revised August 2008 Pipeline The pipeline flow for C28x instructions is identical to that of the C28x CPU described in TMS320C28x DSP CPU and Instruction Set Reference Guide (SPRU430). Some floating-point instructions, however, use additional execution phases and thus require a delay to allow the operation to complete.

  • Page 22: Pipeline Overview

    Pipeline Overview www.ti.com Pipeline Overview The C28x FPU pipeline is identical to the C28x pipeline for all standard C28x instructions. In the decode2 stage (D2), it is determined if an instruction is a C28x instruction or a floating-point unit instruction. The pipeline flow is shown in Figure 3-1.

  • Page 23: Moves From Fpu Registers To C28X Registers

    Moves from FPU Registers to C28x Registers www.ti.com Example 3-1. 2p Instruction Pipeline Alignment ADDF32 R0H, #1.5, R1H ; 2 pipeline cycles (2p) ; 1 cycle delay or non-conflicting instruction ; <-- ADDF32 completes, R0H updated ; Any instruction Moves from FPU Registers to C28x Registers When transferring from the floating-point unit registers to the C28x CPU registers, additional pipeline alignment is required as shown in Example 3-2...

  • Page 24: Parallel Instructions

    Parallel Instructions www.ti.com Parallel Instructions Parallel instructions are single opcodes that perform two operations in parallel. This can be a math operation in parallel with a move operation, or two math operations in parallel. Math operations with a parallel move are referred to as 2p/1 instructions. The math portion of the operation takes 2 pipelined cycles while the move portion of the operation is single cycle.
  • Page 25 Invalid Delay Instructions www.ti.com Example 3-7. Destination Register Conflict ; Invalid delay instruction. Both instructions use the same destination register MPYF32 R2H, R1H, R0H ; 2p instruction MOV32 R2H, mem32 ; Invalid delay instruction Example 3-8. Destination Register Conflict Resolved ;...
  • Page 26 Invalid Delay Instructions www.ti.com Example 3-11. Parallel Instruction Destination/Source Exception ; Valid parallel operation. MPYF32 R2H, R1H, R0H ; 2p/1 instruction || MOV32 mem32, R2H ; <-- Uses R2H before the MPYF32 ; <-- mem32 updated ; <-- Delay for MPYF32 ;...

  • Page 27: Optimizing The Pipeline

    Optimizing the Pipeline www.ti.com Optimizing the Pipeline The following example shows how delay slots can be used to improve the performance of an algorithm. The example performs two Y = MX+B operations. In Example 3-14 , no optimization has been done. The Y = MX+B calculations are sequential and each takes 7 cycles to complete.
  • Page 28 Optimizing the Pipeline www.ti.com Example 3-15. Floating-Point Code With Pipeline Optimization ; Using non-conflicting instructions for alignment cycles, ; calculate the following: ; Y1 = M1*X1 + B1 ; Y2 = M2*X2 + B2 MOV32 R2H,@X1 ; Load R2H with X1 - single cycle MOV32 R1H,@M1 ;...

  • Page 29: Instruction Set

    Chapter 4 SPRUEO2A – June 2007 – Revised August 2008 Instruction Set This chapter describes the assembly language instructions of the TMS320C28x plus floating-point processor. Also described are parallel operations, conditional operations, resource constraints, and addressing modes. The instructions listed here are an extension to the standard C28x instruction set. For information on standard C28x instructions, see the TMS320C28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430).

  • Page 30: Instruction Descriptions

    Instruction Descriptions www.ti.com Instruction Descriptions This section gives detailed information on the instruction set. Each instruction may present the following information: • Operands • Opcode • Description • Exceptions • Pipeline • Examples • See also The example INSTRUCTION is shown to familiarize you with the way each instruction is described. The example describes the kind of information you will find in each part of the individual instruction description and where to obtain more information.
  • Page 31 Instruction Descriptions www.ti.com INSTRUCTION dest1, source1, source2 Short Description Operands dest1 description for the 1st operand for the instruction source1 description for the 2nd operand for the instruction source2 description for the 3rd operand for the instruction Each instruction has a table that gives a list of the operands and a short description. Instructions always have their destination operand(s) first followed by the source operand(s).

  • Page 32: Instructions

    Instructions www.ti.com Instructions The instructions are listed alphabetically, preceded by a summary. Table 4-2. Summary of Instructions ............................Title Page ................ABSF32 RaH, RbH 32-bit Floating-Point Absolute Value ............... ADDF32 RaH, #16FHi, RbH 32-bit Floating-Point Addition ................ ADDF32 RaH, RbH, #16FHi 32-bit Floating-Point Addition ................
  • Page 33 Instructions www.ti.com Table 4-2. Summary of Instructions (continued) ................MOV32 RaH, RbH {, CNDF} Conditional 32-bit Move ......... MOV32 RaH, XARn Move the Contents of XARn to a 32-bit Floating-Point Register ..........MOV32 RaH, XT Move the Contents of XT to a 32-bit Floating-Point Register ............

  • Page 34: Absf32 Rah, Rbh 32-Bit Floating-Point Absolute Value

    Instructions www.ti.com ABSF32 RaH, RbH 32-bit Floating-Point Absolute Value Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1001 0101 MSW: 0000 0000 00bb baaa The absolute value of RbH is loaded into RaH. Only the sign bit of the operand is Description modified by the ABSF32 instruction.

  • Page 35: Addf32 Rah, #16Fhi, Rbh 32-Bit Floating-Point Addition

    Instructions www.ti.com ADDF32 RaH, #16FHi, RbH 32-bit Floating-Point Addition Operands floating-point destination register (R0H to R7H) #16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. floating-point source register (R0H to R7H) Opcode LSW: 1110 1000...
  • Page 36 Instructions www.ti.com ADDF32 RaH, RbH, #16FHi See also ADDF32 RaH, RbH, RcH ADDF32 RdH, ReH, RfH || MOV32 RaH, mem32 ADDF32 RdH, ReH, RfH || MOV32 mem32, RaH MACF32 R3H, R2H, RdH, ReH, RfH MPYF32 RaH, RbH, RcH || ADDF32 RdH, ReH, RfH Instruction Set SPRUEO2A –...

  • Page 37: Addf32 Rah, Rbh, #16Fhi 32-Bit Floating-Point Addition

    Instructions www.ti.com ADDF32 RaH, RbH, #16FHi 32-bit Floating-Point Addition Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) #16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. Opcode LSW: 1110 1000 10II IIII...
  • Page 38 Instructions www.ti.com ADDF32 RaH, #16FHi, RbH See also ADDF32 RaH, RbH, RcH ADDF32 RdH, ReH, RfH || MOV32 RaH, mem32 ADDF32 RdH, ReH, RfH || MOV32 mem32, RaH MACF32 R3H, R2H, RdH, ReH, RfH MPYF32 RaH, RbH, RcH || ADDF32 RdH, ReH, RfH Instruction Set SPRUEO2A –...

  • Page 39: Addf32 Rah, Rbh, Rch 32-Bit Floating-Point Addition

    Instructions www.ti.com ADDF32 RaH, RbH, RcH 32-bit Floating-Point Addition Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0111 0001 0000 MSW: 0000 000c ccbb baaa Add the contents of RcH to the contents of RbH and load the result into RaH. Description RaH = RbH + RcH This instruction modifies the following flags in the STF register:...

  • Page 40: Addf32 Rdh, Reh, Rfh Mov32 Mem32, Rah 32-Bit Floating-Point Addition With Parallel Move

    Instructions www.ti.com ADDF32 RdH, ReH, RfH MOV32 mem32, RaH 32-bit Floating-Point Addition with Parallel Move Operands floating-point destination register for the ADDF32 (R0H to R7H) floating-point source register for the ADDF32 (R0H to R7H) floating-point source register for the ADDF32 (R0H to R7H) mem32 pointer to a 32-bit memory location.
  • Page 41 Instructions www.ti.com ADDF32 RaH, #16FHi, RbH See also ADDF32 RaH, RbH, #16FHi ADDF32 RaH, RbH, RcH MACF32 R3H, R2H, RdH, ReH, RfH MPYF32 RaH, RbH, RcH || ADDF32 RdH, ReH, RfH ADDF32 RdH, ReH, RfH || MOV32 RaH, mem32 SPRUEO2A – June 2007 – Revised August 2008 Instruction Set Submit Documentation Feedback...

  • Page 42: Addf32 Rdh, Reh, Rfh Mov32 Rah, Mem32 32-Bit Floating-Point Addition With Parallel Move

    Instructions www.ti.com ADDF32 RdH, ReH, RfH MOV32 RaH, mem32 32-bit Floating-Point Addition with Parallel Move Operands floating-point destination register for the ADDF32 (R0H to R7H). RdH cannot be the same register as RaH. floating-point source register for the ADDF32 (R0H to R7H) floating-point source register for the ADDF32 (R0H to R7H) floating-point destination register for the MOV32 (R0H to R7H).
  • Page 43 Instructions www.ti.com Calculate Y = A + B - C: Example MOVL XAR4, #A MOV32 R0H, *XAR4 ; Load R0H with A MOVL XAR4, #B MOV32 R1H, *XAR4 ; Load R1H with B MOVL XAR4, #C ADDF32 R0H,R1H,R0H ; Add A + B and in parallel || MOV32 R2H, *XAR4 ;...

  • Page 44: Cmpf32 Rah, Rbh 32-Bit Floating-Point Compare For Equal, Less Than Or Greater Than

    Instructions www.ti.com CMPF32 RaH, RbH 32-bit Floating-Point Compare for Equal, Less Than or Greater Than Operands floating-point source register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1001 0100 MSW: 0000 0000 00bb baaa Set ZF and NF flags on the result of RaH - RbH. The CMPF32 instruction is performed Description as a logical compare operation.

  • Page 45: Cmpf32 Rah, #16Fhi 32-Bit Floating-Point Compare For Equal, Less Than Or Greater Than

    Instructions www.ti.com CMPF32 RaH, #16FHi 32-bit Floating-Point Compare for Equal, Less Than or Greater Than Operands floating-point source register (R0H to R7H) #16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. Opcode LSW: 1110 1000 0001 0III...

  • Page 46: Cmpf32 Rah, #0.0 32-Bit Floating-Point Compare For Equal, Less Than Or Greater Than

    Instructions www.ti.com CMPF32 RaH, #0.0 32-bit Floating-Point Compare for Equal, Less Than or Greater Than Operands floating-point source register (R0H to R7H) #0.0 zero Opcode LSW: 1110 0101 1010 0aaa Set the ZF and NF flags on (RaH - #0.0). The CMPF32 instruction is performed as a Description logical compare operation.

  • Page 47: Einvf32 Rah, Rbh 32-Bit Floating-Point Reciprocal Approximation

    Instructions www.ti.com EINVF32 RaH, RbH 32-bit Floating-Point Reciprocal Approximation Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1001 0011 MSW: 0000 0000 00bb baaa This operation generates an estimate of 1/X in 32-bit floating-point format accurate to Description approximately 8 bits.
  • Page 48 Instructions www.ti.com Calculate Y = A/B. A fast division routine similar to that shown below can be found in the Example C28x FPU Fast RTS Library (SPRC664). MOVL XAR4, #A MOV32 R0H, *XAR4 ; Load R0H with A MOVL XAR4, #B MOV32 R1H, *XAR4 ;...

  • Page 49: Eisqrtf32 Rah, Rbh 32-Bit Floating-Point Square-Root Reciprocal Approximation

    Instructions www.ti.com EISQRTF32 RaH, RbH 32-bit Floating-Point Square-Root Reciprocal Approximation Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1001 0010 MSW: 0000 0000 00bb baaa This operation generates an estimate of 1/sqrt(X) in 32-bit floating-point format accurate Description to approximately 8 bits.
  • Page 50 Instructions www.ti.com Calculate the square root of X. A square-root routine similar to that shown below can be Example found in the C28x FPU Fast RTS Library (SPRC664). ; Y = sqrt(X) ; Ye = Estimate(1/sqrt(X)); ; Ye = Ye*(1.5 - Ye*Ye*X*0.5) ;...

  • Page 51: F32Toi16 Rah, Rbh Convert 32-Bit Floating-Point Value To 16-Bit Integer

    Instructions www.ti.com F32TOI16 RaH, RbH Convert 32-bit Floating-Point Value to 16-bit Integer Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1000 1100 MSW: 0000 0000 00bb baaa Convert a 32-bit floating point value in RbH to a 16-bit integer and truncate. The result Description will be stored in RaH.

  • Page 52: F32Toi16R Rah, Rbh Convert 32-Bit Floating-Point Value To 16-Bit Integer And Round

    Instructions www.ti.com F32TOI16R RaH, RbH Convert 32-bit Floating-Point Value to 16-bit Integer and Round Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1000 1100 MSW: 1000 0000 00bb baaa Convert the 32-bit floating point value in RbH to a 16-bit integer and round to the nearest Description even value.

  • Page 53: F32Toi32 Rah, Rbh Convert 32-Bit Floating-Point Value To 32-Bit Integer

    Instructions www.ti.com F32TOI32 RaH, RbH Convert 32-bit Floating-Point Value to 32-bit Integer Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1000 1000 MSW: 0000 0000 00bb baaa Convert the 32-bit floating-point value in RbH to a 32-bit integer value and truncate. Description Store the result in RaH.

  • Page 54: F32Toui16 Rah, Rbh Convert 32-Bit Floating-Point Value To 16-Bit Unsigned Integer

    Instructions www.ti.com F32TOUI16 RaH, RbH Convert 32-bit Floating-Point Value to 16-bit Unsigned Integer Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1000 1110 MSW: 0000 0000 00bb baaa Convert the 32-bit floating point value in RbH to an unsigned 16-bit integer value and Description truncate to zero.

  • Page 55: F32Toui16R Rah, Rbh Convert 32-Bit Floating-Point Value To 16-Bit Unsigned Integer And Round

    Instructions www.ti.com F32TOUI16R RaH, RbH Convert 32-bit Floating-Point Value to 16-bit Unsigned Integer and Round Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1000 1110 MSW: 1000 0000 00bb baaa Convert the 32-bit floating-point value in RbH to an unsigned 16-bit integer and round to Description the closest even value.

  • Page 56: F32Toui32 Rah, Rbh Convert 32-Bit Floating-Point Value To 16-Bit Unsigned Integer

    Instructions www.ti.com F32TOUI32 RaH, RbH Convert 32-bit Floating-Point Value to 16-bit Unsigned Integer Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1000 1010 MSW: 0000 0000 00bb baaa Convert the 32-bit floating-point value in RbH to an unsigned 32-bit integer and store the Description result in RaH.

  • Page 57: Fracf32 Rah, Rbh Fractional Portion Of A 32-Bit Floating-Point Value

    Instructions www.ti.com FRACF32 RaH, RbH Fractional Portion of a 32-bit Floating-Point Value Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1111 0001 MSW: 0000 0000 00bb baaa Returns in RaH the fractional portion of the 32-bit floating-point value in RbH Description This instruction does not affect any flags: Flags...

  • Page 58: I16Tof32 Rah, Rbh Convert 16-Bit Integer To 32-Bit Floating-Point Value

    Instructions www.ti.com I16TOF32 RaH, RbH Convert 16-bit Integer to 32-bit Floating-Point Value Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1000 1101 MSW: 0000 0000 00bb baaa Convert the 16-bit signed integer in RbH to a 32-bit floating point value and store the Description result in RaH.

  • Page 59: I16Tof32 Rah, Mem16 Convert 16-Bit Integer To 32-Bit Floating-Point Value

    Instructions www.ti.com I16TOF32 RaH, mem16 Convert 16-bit Integer to 32-bit Floating-Point Value Operands floating-point destination register (R0H to R7H) mem316 16-bit source memory location to be converted Opcode LSW: 1110 0110 1100 1000 MSW: 0000 0aaa mem16 Convert the 16-bit signed integer indicated by the mem16 pointer to a 32-bit Description floating-point value and store the result in RaH.

  • Page 60: I32Tof32 Rah, Mem32 Convert 32-Bit Integer To 32-Bit Floating-Point Value

    Instructions www.ti.com I32TOF32 RaH, mem32 Convert 32-bit Integer to 32-bit Floating-Point Value Operands floating-point destination register (R0H to R7H) mem32 32-bit source for the MOV32 operation. mem32 means that the operation can only address memory using any of the direct or indirect addressing modes supported by the C28x CPU Opcode LSW: 1110 0010...

  • Page 61: I32Tof32 Rah, Rbh Convert 32-Bit Integer To 32-Bit Floating-Point Value

    Instructions www.ti.com I32TOF32 RaH, RbH Convert 32-bit Integer to 32-bit Floating-Point Value Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1000 1001 MSW: 0000 0000 00bb baaa Convert the signed 32-bit integer in RbH to a 32-bit floating-point value and store the Description result in RaH.

  • Page 62: Macf32 R3H, R2H, Rdh, Reh, Rfh 32-Bit Floating-Point Multiply With Parallel Add

    Instructions www.ti.com MACF32 R3H, R2H, RdH, ReH, RfH 32-bit Floating-Point Multiply with Parallel Add This instruction is an alias for the parallel multiply and add instruction. The operands are Operands translated by the assembler such that the instruction becomes: MPYF32 RdH, RaH, RbH || ADDF32 R3H, R3H, R2H...
  • Page 63 Instructions www.ti.com Example Perform 5 multiply and accumulate operations: 1st multiply: A = X0 * Y0 2nd multiply: B = X1 * Y1 3rd multiply: C = X2 * Y2 4th multiply: D = X3 * Y3 5th multiply: E = X3 * Y3 Result = A + B + C + D + E MOV32 R0H, *XAR4++...

  • Page 64: Move

    Instructions www.ti.com MACF32 R3H, R2H, RdH, ReH, RfH MOV32 RaH, mem32 32-bit Floating-Point Multiply and Accumulate with Parallel Move Operands floating-point destination/source register R3H for the add operation floating-point source register R2H for the add operation floating-point destination register (R0H to R7H) for the multiply operation RdH cannot be the same register as RaH floating-point source register (R0H to R7H) for the multiply operation floating-point source register (R0H to R7H) for the multiply operation...
  • Page 65 Instructions www.ti.com Example Perform 5 multiply and accumulate operations: 1ST multiply: A = X0 * Y0 2nd multiply: B = X1 * Y1 3rd multiply: C = X2 * Y2 4TH multiply: D = X3 * Y3 5th multiply: E = X3 * Y3 Result = A + B + C + D + E MOV32 R0H, *XAR4++...

  • Page 66: Macf32 R7H, R3H, Mem32, *Xar7++ 32-Bit Floating-Point Multiply And Accumulate

    Instructions www.ti.com MACF32 R7H, R3H, mem32, *XAR7++ 32-bit Floating-Point Multiply and Accumulate Operands floating-point destination register floating-point destination register mem32 pointer to a 32-bit source location *XAR7 32-bit location pointed to by auxiliary register 7 Opcode LSW: 1110 0010 0101 0000 MSW: 00bb baaa mem32 Perform an multiply and accumulate operation.
  • Page 67 Instructions www.ti.com MACF32 can also be used standalone. In this case, the insruction takes 2 cycles and the following pipeline restrictions apply: <instruction1> ; No restriction <instruction2> ; Cannot be a 2p instruction that writes ; to R2H, R3H, R6H or R7H MACF32 R7H, R3H, *XAR6, *XAR7 ;...

  • Page 68: Macf32 R7H, R6H, Rdh, Reh, Rfh 32-Bit Floating-Point Multiply With Parallel Add

    Instructions www.ti.com MACF32 R7H, R6H, RdH, ReH, RfH 32-bit Floating-Point Multiply with Parallel Add This instruction is an alias for the parallel multiply and add instruction. The operands are Operands translated by the assembler such that the instruction becomes: MPYF32 RdH, RaH, RbH || ADDF32 R7H, R7H, R6H...
  • Page 69 Instructions www.ti.com Example Perform 5 multiply and accumulate operations: 1st multiply: A = X0 * Y0 2nd multiply: B = X1 * Y1 3rd multiply: C = X2 * Y2 4th multiply: D = X3 * Y3 5th multiply: E = X3 * Y3 Result = A + B + C + D + E MOV32 R0H, *XAR4++...

  • Page 70: Move

    Instructions www.ti.com MACF32 R7H, R6H, RdH, ReH, RfH MOV32 RaH, mem32 32-bit Floating-Point Multiply and Accumulate with Parallel Move Operands floating-point destination/source register R7H for the add operation floating-point source register R6H for the add operation floating-point destination register (R0H to R7H) for the multiply operation. RdH cannot be the same register as RaH.
  • Page 71 Instructions www.ti.com Example Perform 5 multiply and accumulate operations: 1st multiply: A = X0 * Y0 2nd multiply: B = X1 * Y1 3rd multiply: C = X2 * Y2 4th multiply: D = X3 * Y3 5th multiply: E = X3 * Y3 Result = A + B + C + D + E MOV32 R0H, *XAR4++...

  • Page 72: Maxf32 Rah, Rbh 32-Bit Floating-Point Maximum

    Instructions www.ti.com MAXF32 RaH, RbH 32-bit Floating-Point Maximum Operands floating-point source/destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1001 0110 MSW: 0000 0000 00bb baaa Description if(RaH < RbH) RaH = RbH Special cases for the output from the MAXF32 operation: •...

  • Page 73: Maxf32 Rah, #16Fhi 32-Bit Floating-Point Maximum

    Instructions www.ti.com MAXF32 RaH, #16FHi 32-bit Floating-Point Maximum Operands floating-point source/destination register (R0H to R7H) #16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. Opcode LSW: 1110 1000 0010 0III...

  • Page 74: Maxf32 Rah, Rbh Mov32 Rch, Rdh 32-Bit Floating-Point Maximum With Parallel Move

    Instructions www.ti.com MAXF32 RaH, RbH MOV32 RcH, RdH 32-bit Floating-Point Maximum with Parallel Move Operands floating-point source/destination register for the MAXF32 operation (R0H to R7H) RaH cannot be the same register as RcH floating-point source register for the MAXF32 operation (R0H to R7H) floating-point destination register for the MOV32 operation (R0H to R7H) RcH cannot be the same register as RaH floating-point source register for the MOV32 operation (R0H to R7H)

  • Page 75: Minf32 Rah, Rbh 32-Bit Floating-Point Minimum

    Instructions www.ti.com MINF32 RaH, RbH 32-bit Floating-Point Minimum Operands floating-point source/destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1001 0111 MSW: 0000 0000 00bb baaa Description if(RaH > RbH) RaH = RbH Special cases for the output from the MINF32 operation: •...

  • Page 76: Minf32 Rah, #16Fhi 32-Bit Floating-Point Minimum

    Instructions www.ti.com MINF32 RaH, #16FHi 32-bit Floating-Point Minimum Operands floating-point source/destination register (R0H to R7H) #16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. Opcode LSW: 1110 1000 0011 0III...

  • Page 77: Minf32 Rah, Rbh Mov32 Rch, Rdh 32-Bit Floating-Point Minimum With Parallel Move

    Instructions www.ti.com MINF32 RaH, RbH MOV32 RcH, RdH 32-bit Floating-Point Minimum with Parallel Move Operands floating-point source/destination register for the MIN32 operation (R0H to R7H) RaH cannot be the same register as RcH floating-point source register for the MIN32 operation (R0H to R7H) floating-point destination register for the MOV32 operation (R0H to R7H) RcH cannot be the same register as RaH floating-point source register for the MOV32 operation (R0H to R7H)

  • Page 78: Mov16 Mem16, Rah Move 16-Bit Floating-Point Register Contents To Memory

    Instructions www.ti.com MOV16 mem16, RaH Move 16-bit Floating-Point Register Contents to Memory Operands mem16 points to the 16-bit destination memory floating-point source register (R0H to R7H) Opcode LSW: 1110 0010 0001 0011 MSW: 0000 0aaa mem16 Move 16-bit value from the lower 16-bits of the floating-point register (RaH[15:0]) to the Description location pointed to by mem16.

  • Page 79: Mov32 *(0:16Bitaddr), Loc32 Move The Contents Of Loc32 To Memory

    Instructions www.ti.com MOV32 *(0:16bitAddr), loc32 Move the Contents of loc32 to Memory Operands 0:16bitAddr 16-bit immediate address, zero extended loc32 32 bit source location Opcode LSW: 1011 1101 loc32 MSW: IIII IIII IIII IIII Move the 32-bit value in loc32 to the memory location addressed by 0:16bitAddr. The Description EALLOW bit in the ST1 register is ignored by this operation.

  • Page 80: Mov32 Acc, Rah Move 32-Bit Floating-Point Register Contents To Acc

    Instructions www.ti.com MOV32 ACC, RaH Move 32-bit Floating-Point Register Contents to ACC Operands 28x accumulator floating-point source register (R0H to R7H) Opcode LSW: 1011 1111 loc32 MSW: IIII IIII IIII IIII If the condition is true, then move the 32-bit value referenced by mem32 to the Description floating-point register indicated by RaH.

  • Page 81: Mov32 Loc32, *(0:16Bitaddr) Move 32-Bit Value From Memory To Loc32

    Instructions www.ti.com MOV32 loc32, *(0:16bitAddr) Move 32-bit Value from Memory to loc32 Operands loc32 destination location 0:16bitAddr 16-bit address of the 32-bit source value Opcode LSW: 1011 1111 loc32 MSW: IIII IIII IIII IIII Copy the 32-bit value referenced by 0:16bitAddr to the location indicated by loc32. Description [loc32] = [0:16bitAddr] No STF flags are affected.

  • Page 82: Mov32 Mem32, Rah Move 32-Bit Floating-Point Register Contents To Memory

    Instructions www.ti.com MOV32 mem32, RaH Move 32-bit Floating-Point Register Contents to Memory Operands floating-point register (R0H to R7H) mem32 points to the 32-bit destination memory Opcode LSW: 1110 0010 0000 0011 MSW: 0000 0aaa mem32 Move from memory to STF. Description [mem32] = RaH This instruction modifies the following flags in the STF register:...

  • Page 83: Mov32 Mem32, Stf Move 32-Bit Stf Register To Memory

    Instructions www.ti.com MOV32 mem32, STF Move 32-bit STF Register to Memory Operands floating-point status register mem32 points to the 32-bit destination memory Opcode LSW: 1110 0010 0000 0000 MSW: 0000 0000 mem32 Copy the floating-point status register, STF, to memory. Description [mem32] = STF This instruction modifies the following flags in the STF register:...

  • Page 84: Mov32 P, Rah Move 32-Bit Floating-Point Register Contents To P

    Instructions www.ti.com MOV32 P, RaH Move 32-bit Floating-Point Register Contents to P Operands 28x product register P floating-point source register (R0H to R7H) Opcode LSW: 1011 1111 loc32 MSW: IIII IIII IIII IIII Move the 32-bit value in RaH to the 28x product register P. Description P = RaH No flags affected in floating-point unit.

  • Page 85: Mov32 Rah, Acc Move The Contents Of Acc To A 32-Bit Floating-Point Register

    Instructions www.ti.com MOV32 RaH, ACC Move the Contents of ACC to a 32-bit Floating-Point Register Operands floating-point destination register (R0H to R7H) accumulator Opcode LSW: 1011 1101 loc32 MSW: IIII IIII IIII IIII Move the 32-bit value in ACC to the floating-point register RaH. Description RaH = ACC This instruction does not modify any STF register flags.

  • Page 86: Mov32 Rah, Mem32 {, Cndf} Conditional 32-Bit Move

    Instructions www.ti.com MOV32 RaH, mem32 {, CNDF} Conditional 32-bit Move Operands floating-point destination register (R0H to R7H) mem32 pointer to the 32-bit source memory location CNDF optional condition. Opcode LSW: 1110 0010 1010 CNDF MSW: 0000 0aaa mem32 If the condition is true, then move the 32-bit value referenced by mem32 to the Description floating-point register indicated by RaH.
  • Page 87 Instructions www.ti.com Example MOVW DP, #0x0300 ; DP = 0x0300 @0, #0x5555 ; [0x00C000] = 0x5555 @1, #0x5555 ; [0x00C001] = 0x5555 MOVIZF32 R3H, #7.0 ; R3H = 7.0 (0x40E00000) MOVIZF32 R4H, #7.0 ; R4H = 7.0 (0x40E00000) MAXF32 R3H, R4H ;...

  • Page 88: Mov32 Rah, P Move The Contents Of P To A 32-Bit Floating-Point Register

    Instructions www.ti.com MOV32 RaH, P Move the Contents of P to a 32-bit Floating-Point Register Operands floating-point register (R0H to R7H) product register Opcode LSW: 1011 1101 loc32 MSW: IIII IIII IIII IIII Move the 32-bit value in the product register, P, to the floating-point register RaH. Description RaH = P This instruction does not modify any STF register flags.

  • Page 89: Mov32 Rah, Rbh {, Cndf} Conditional 32-Bit Move

    Instructions www.ti.com MOV32 RaH, RbH {, CNDF} Conditional 32-bit Move Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) CNDF optional condition. Opcode LSW: 1110 0110 1100 CNDF MSW: 0000 0000 00bb baaa If the condition is true, then move the 32-bit value referenced by mem32 to the Description floating-point register indicated by RaH.

  • Page 90: Mov32 Rah, Xarn Move The Contents Of Xarn To A 32-Bit Floating-Point Register

    Instructions www.ti.com MOV32 RaH, XARn Move the Contents of XARn to a 32-bit Floating-Point Register Operands floating-point register (R0H to R7H) XARn auxiliary register (XAR0 - XAR7) Opcode LSW: 1011 1101 loc32 MSW: IIII IIII IIII IIII Move the 32-bit value in the auxiliary register XARn to the floating point register RaH. Description RaH = XARn This instruction does not modify any STF register flags.

  • Page 91: Mov32 Rah, Xt Move The Contents Of Xt To A 32-Bit Floating-Point Register

    Instructions www.ti.com MOV32 RaH, XT Move the Contents of XT to a 32-bit Floating-Point Register Operands floating-point register (R0H to R7H) auxiliary register (XAR0 - XAR7) Opcode LSW: 1011 1101 loc32 MSW: IIII IIII IIII IIII Move the 32-bit value in temporary register, XT, to the floating-point register RaH. Description RaH = XT This instruction does not modify any STF register flags.

  • Page 92: Mov32 Stf, Mem32 Move 32-Bit Value From Memory To The Stf Register

    Instructions www.ti.com MOV32 STF, mem32 Move 32-bit Value from Memory to the STF Register Operands floating-point unit status register mem32 pointer to the 32-bit source memory location Opcode LSW: 1110 0010 1000 0000 MSW: 0000 0000 mem32 Move from memory to the floating-point unit's status register STF. Description STF = [mem32] This instruction modifies the following flags in the STF register:...

  • Page 93: Mov32 Xarn, Rah Move 32-Bit Floating-Point Register Contents To Xarn

    Instructions www.ti.com MOV32 XARn, RaH Move 32-bit Floating-Point Register Contents to XARn Operands XARn 28x auxiliary register (XAR0 - XAR7) floating-point source register (R0H to R7H) Opcode LSW: 1011 1111 loc32 MSW: IIII IIII IIII IIII Move the 32-bit value from the floating-point register RaH to the auxiliary register XARn. Description XARn = RaH No flags affected in floating-point unit.

  • Page 94: Mov32 Xt, Rah Move 32-Bit Floating-Point Register Contents To Xt

    Instructions www.ti.com MOV32 XT, RaH Move 32-bit Floating-Point Register Contents to XT Operands temporary register floating-point source register (R0H to R7H) Opcode LSW: 1011 1111 loc32 MSW: IIII IIII IIII IIII Move the 32-bit value in RaH to the temporary register XT. Description XT = RaH No flags affected in floating-point unit.

  • Page 95: Movd32 Rah, Mem32 Move 32-Bit Value From Memory With Data Copy

    Instructions www.ti.com MOVD32 RaH, mem32 Move 32-bit Value from Memory with Data Copy Operands floating-point register (R0H to R7H) mem32 pointer to the 32-bit source memory location Opcode LSW: 1110 0010 0010 0011 MSW: 0000 0aaa mem32 Move the 32-bit value referenced by mem32 to the floating-point register indicated by Description RaH.

  • Page 96: Movf32 Rah, #32F Load The 32-Bits Of A 32-Bit Floating-Point Register

    Instructions www.ti.com MOVF32 RaH, #32F Load the 32-bits of a 32-bit Floating-Point Register This instruction is an alias for MOVIZ and MOVXI instructions. The second operand is Operands translated by the assembler such that the instruction becomes: MOVIZ RaH, #16FHiHex MOVXI RaH, #16FLoHex floating-point destination register (R0H to R7H) #32F...

  • Page 97: Movi32 Rah, #32Fhex Load The 32-Bits Of A 32-Bit Floating-Point Register With The Immediate

    Instructions www.ti.com MOVI32 RaH, #32FHex Load the 32-bits of a 32-bit Floating-Point Register with the immediate This instruction is an alias for MOVIZ and MOVXI instructions. The second operand is Operands translated by the assembler such that the instruction becomes: MOVIZ RaH, #16FHiHex MOVXI RaH, #16FLoHex floating-point register (R0H to R7H)

  • Page 98: Moviz Rah, #16Fhihex Load The Upper 16-Bits Of A 32-Bit Floating-Point Register

    Instructions www.ti.com MOVIZ RaH, #16FHiHex Load the Upper 16-bits of a 32-bit Floating-Point Register Operands floating-point register (R0H to R7H) #16FHiHex A 16-bit immediate hex value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. Opcode LSW: 1110 1000 0000 0III...

  • Page 99: Movizf32 Rah, #16Fhi Load The Upper 16-Bits Of A 32-Bit Floating-Point Register

    Instructions www.ti.com MOVIZF32 RaH, #16FHi Load the Upper 16-bits of a 32-bit Floating-Point Register Operands floating-point register (R0H to R7H) #16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. Opcode LSW: 1110 1000 0000 0III...

  • Page 100: Movst0 Flag Load Selected Stf Flags Into St0

    Instructions www.ti.com MOVST0 FLAG Load Selected STF Flags into ST0 Operands FLAG Selected flag Opcode LSW: 1010 1101 FFFF FFFF Load selected flags from the STF register into the ST0 register of the 28x CPU where Description FLAG is one or more of TF, CI, ZI, ZF, NI, NF, LUF or LVF. The specified flag maps to the ST0 register as follows: •...

  • Page 101: Movxi Rah, #16Flohex Move Immediate To The Low 16-Bits Of A Floating-Point Register

    Instructions www.ti.com MOVXI RaH, #16FLoHex Move Immediate to the Low 16-bits of a Floating-Point Register Operands floating-point register (R0H to R7H) #16FLoHex A 16-bit immediate hex value that represents the lower 16-bits of an IEEE 32-bit floating-point value. The upper 16-bits will not be modified. Opcode LSW: 1110 1000 0000 1III...

  • Page 102: Mpyf32 Rah, Rbh, Rch 32-Bit Floating-Point Multiply

    Instructions www.ti.com MPYF32 RaH, RbH, RcH 32-bit Floating-Point Multiply Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0111 0000 0000 MSW: 0000 000c ccbb baaa Multiply the contents of two floating-point registers. Description RaH = RbH * RcH This instruction modifies the following flags in the STF register:.

  • Page 103: Mpyf32 Rah, #16Fhi, Rbh 32-Bit Floating-Point Multiply

    Instructions www.ti.com MPYF32 RaH, #16FHi, RbH 32-bit Floating-Point Multiply Operands floating-point destination register (R0H to R7H) #16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. floating-point source register (R0H to R7H) Opcode LSW: 1110 1000...

  • Page 104: Mpyf32 Rah, Rbh, #16Fhi 32-Bit Floating-Point Multiply

    Instructions www.ti.com MPYF32 RaH, RbH, #16FHi 32-bit Floating-Point Multiply Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) #16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. Opcode LSW: 1110 1000 01II IIII...

  • Page 105: Mpyf32 Rah, Rbh, Rch Addf32 Rdh, Reh, Rfh 32-Bit Floating-Point Multiply With Parallel Add

    Instructions www.ti.com MPYF32 RaH, RbH, RcH ADDF32 RdH, ReH, RfH 32-bit Floating-Point Multiply with Parallel Add Operands floating-point destination register for MPYF32 (R0H to R7H) RaH cannot be the same register as RdH floating-point source register for MPYF32 (R0H to R7H) floating-point source register for MPYF32 (R0H to R7H) floating-point destination register for ADDF32 (R0H to R7H) RdH cannot be the same register as RaH...
  • Page 106 Instructions www.ti.com Example Perform 5 multiply and accumulate operations: 1st multiply: A = X0 * Y0 2nd multiply: B = X1 * Y1 3rd multiply: C = X2 * Y2 4th multiply: D = X3 * Y3 5th multiply: E = X3 * Y3 Result = A + B + C + D + E MOV32 R0H, *XAR4++...

  • Page 107: Mpyf32 Rdh, Reh, Rfh Mov32 Rah, Mem32 32-Bit Floating-Point Multiply With Parallel Move

    Instructions www.ti.com MPYF32 RdH, ReH, RfH MOV32 RaH, mem32 32-bit Floating-Point Multiply with Parallel Move Operands floating-point destination register for the MPYF32 (R0H to R7H) RdH cannot be the same register as RaH floating-point source register for the MPYF32 (R0H to R7H) floating-point source register for the MPYF32 (R0H to R7H) floating-point destination register for the MOV32 (R0H to R7H) RaH cannot be the same register as RdH...
  • Page 108 Instructions www.ti.com Calculate Y = M1*X1 + B1. This example assumes that M1, X1, B1 and Y1 are all on the Example same data page. MOVW DP, #M1 ; Load the data page MOV32 R0H,@M1 ; Load R0H with M1 MOV32 R1H,@X1 ;...

  • Page 109: Mpyf32 Rdh, Reh, Rfh Mov32 Mem32, Rah 32-Bit Floating-Point Multiply With Parallel Move

    Instructions www.ti.com MPYF32 RdH, ReH, RfH MOV32 mem32, RaH 32-bit Floating-Point Multiply with Parallel Move Operands floating-point destination register for the MPYF32 (R0H to R7H) floating-point source register for the MPYF32 (R0H to R7H) floating-point source register for the MPYF32 (R0H to R7H) mem32 pointer to a 32-bit memory location.

  • Page 110: Mpyf32 Rah, Rbh, Rch Subf32 Rdh, Reh, Rfh 32-Bit Floating-Point Multiply With Parallel Subtract

    Instructions www.ti.com MPYF32 RaH, RbH, RcH SUBF32 RdH, ReH, RfH 32-bit Floating-Point Multiply with Parallel Subtract Operands floating-point destination register for MPYF32 (R0H to R7H) RaH cannot be the same register as RdH floating-point source register for MPYF32 (R0H to R7H) floating-point source register for MPYF32 (R0H to R7H) floating-point destination register for SUBF32 (R0H to R7H) RdH cannot be the same register as RaH...

  • Page 111: Negf32 Rah, Rbh{, Cndf} Conditional Negation

    Instructions www.ti.com NEGF32 RaH, RbH{, CNDF} Conditional Negation Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) CNDF condition tested Opcode LSW: 1110 0110 1010 CNDF MSW: 0000 0000 00bb baaa Description if (CNDF == true) {RaH = - RbH } else {RaH = RbH } CNDF is one of the following conditions:...

  • Page 112: Pop Rb Pop The Rb Register From The Stack

    Instructions www.ti.com POP RB Pop the RB Register from the Stack Operands repeat block register Opcode LSW: 1111 1111 1111 0001 Restore the RB register from stack. If a high-priority interrupt contains a RPTB Description instruction, then the RB register must be stored on the stack before the RPTB block and restored after the RTPB block.

  • Page 113: Push Rb Push The Rb Register Onto The Stack

    Instructions www.ti.com PUSH RB Push the RB Register onto the Stack Operands repeat block register Opcode LSW: 1111 1111 1111 0000 Save the RB register on the stack. If a high-priority interrupt contains a RPTB instruction, Description then the RB register must be stored on the stack before the RPTB block and restored after the RTPB block.

  • Page 114: Restore Restore The Floating-Point Registers

    Instructions www.ti.com RESTORE Restore the Floating-Point Registers Operands none This instruction does not have any operands Opcode LSW: 1110 0101 0110 0010 Restore the floating-point register set (R0H - R7H and STF) from their shadow registers. Description The SAVE and RESTORE instructions should be used in high-priority interrupts. That is interrupts that cannot themselves be interrupted.
  • Page 115 Instructions www.ti.com The following example shows a complete context save and restore for a high-priority Example interrupt. Note that the CPU automatically stores the following registers: ACC, P, XT, ST0, ST1, IER, DP, AR0, AR1 and PC. If an interrupt is low priority (that is it can be interrupted), then push the floating point registers onto the stack instead of using the SAVE and RESTORE operations.

  • Page 116: Rptb Label, Loc16 Repeat A Block Of Code

    Instructions www.ti.com RPTB label, loc16 Repeat A Block of Code Operands label This label is used by the assembler to determine the end of the repeat block and to calculate RSIZE. This label should be placed immediately after the last instruction included in the repeat block.
  • Page 117 Instructions www.ti.com have to save the RB register. ; Repeat Block within a High-Priority Interrupt (Non-Interruptible) ; Interrupt: ; RAS = RA, RA = 0 PUSH RB ; Save RB register only if a RPTB block is used in the RPTB #BlockEnd, AL ;...

  • Page 118: Rptb Label, #Rc Repeat A Block Of Code

    Instructions www.ti.com RPTB label, #RC Repeat a Block of Code Operands label This label is used by the assembler to determine the end of the repeat block and to calculate RSIZE. This label should be placed immediately after the last instruction included in the repeat block.
  • Page 119 Instructions www.ti.com have to save the RB register. ; Repeat Block within a High-Priority Interrupt (Non-Interruptible) ; Interrupt: ; RAS = RA, RA = 0 PUSH RB ; Save RB register only if a RPTB block is used in the RPTB #BlockEnd, #5 ;...

  • Page 120: Save Flag, Value Save Register Set To Shadow Registers And Execute Setflg

    Instructions www.ti.com SAVE FLAG, VALUE Save Register Set to Shadow Registers and Execute SETFLG Operands FLAG 11 bit mask indicating which floating-point status flags to change. VALUE 11 bit mask indicating the flag value; 0 or 1. Opcode LSW: 1110 0110 01FF FFFF MSW: FFFF FVVV VVVV VVVV...
  • Page 121 Instructions www.ti.com _HighestPriorityISR: ; Align stack PUSH ; Save RB register if used in the ISR PUSH AR1H:AR0H ; Save other registers if used PUSH XAR2 PUSH XAR3 PUSH XAR4 PUSH XAR5 PUSH XAR6 PUSH XAR7 PUSH ; Set default C28 modes CLRC AMODE CLRC...

  • Page 122: Setflg Flag, Value Set Or Clear Selected Floating-Point Status Flags

    Instructions www.ti.com SETFLG FLAG, VALUE Set or clear selected floating-point status flags Operands FLAG 11 bit mask indicating which floating-point status flags to change. VALUE 11 bit mask indicating the flag value; 0 or 1. Opcode LSW: 1110 0110 00FF FFFF MSW: FFFF FVVV VVVV VVVV The SETFLG instruction is used to set or clear selected floating-point status flags in the...

  • Page 123: Subf32 Rah, Rbh, Rch 32-Bit Floating-Point Subtraction

    Instructions www.ti.com SUBF32 RaH, RbH, RcH 32-bit Floating-Point Subtraction Operands floating-point destination register (R0H to R1) floating-point source register (R0H to R1) floating-point source register (R0H to R1) Opcode LSW: 1110 0111 0010 0000 MSW: 0000 000c ccbb baaa Subtract the contents of two floating-point registers Description RaH = RbH - RcH This instruction modifies the following flags in the STF register:...

  • Page 124: Subf32 Rah, #16Fhi, Rbh 32-Bit Floating Point Subtraction

    Instructions www.ti.com SUBF32 RaH, #16FHi, RbH 32-bit Floating Point Subtraction Operands floating-point destination register (R0H to R1) #16FHi A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. floating-point source register (R0H to R1) Opcode LSW: 1110 1000...

  • Page 125: Subf32 Rdh, Reh, Rfh Mov32 Rah, Mem32 32-Bit Floating-Point Subtraction With Parallel Move

    Instructions www.ti.com SUBF32 RdH, ReH, RfH MOV32 RaH, mem32 32-bit Floating-Point Subtraction with Parallel Move Operands floating-point destination register (R0H to R7H) for the SUBF32 operation RdH cannot be the same register as RaH floating-point source register (R0H to R7H) for the SUBF32 operation floating-point source register (R0H to R7H) for the SUBF32 operation floating-point destination register (R0H to R7H) for the MOV32 operation RaH cannot be the same register as RdH...
  • Page 126 Instructions www.ti.com Example MOVL XAR1, #0xC000 ; XAR1 = 0xC000 SUBF32 R0H, R1H, R2H ; (A) R0H = R1H - R2H || MOV32 R3H, *XAR1 ; <-- R3H valid MOV32 R4H, *+XAR1[2] ; ; <-- (A) completes, R0H valid, R4H valid ADDF32 R5H, R4H, R3H ;...

  • Page 127: Subf32 Rdh, Reh, Rfh Mov32 Mem32, Rah 32-Bit Floating-Point Subtraction With Parallel Move

    Instructions www.ti.com SUBF32 RdH, ReH, RfH MOV32 mem32, RaH 32-bit Floating-Point Subtraction with Parallel Move Operands floating-point destination register (R0H to R7H) for the SUBF32 operation floating-point source register (R0H to R7H) for the SUBF32 operation floating-point source register (R0H to R7H) for the SUBF32 operation mem32 pointer to 32-bit destination memory location for the MOV32 operation floating-point source register (R0H to R7H) for the MOV32 operation...

  • Page 128: Swapf Rah, Rbh{, Cndf} Conditional Swap

    Instructions www.ti.com SWAPF RaH, RbH{, CNDF} Conditional Swap Operands floating-point register (R0H to R7H) floating-point register (R0H to R7H) CNDF condition tested Opcode LSW: 1110 0110 1110 CNDF MSW: 0000 0000 00bb baaa Conditional swap of RaH and RbH. Description if (CNDF == true) swap RaH and RbH CNDF is one of the following conditions: Encode...

  • Page 129: Testtf Cndf Test Stf Register Flag Condition

    Instructions www.ti.com TESTTF CNDF Test STF Register Flag Condition Operands CNDF condition to test Opcode LSW: 1110 0101 1000 CNDF Test the floating-point condition and if true, set the TF flag. If the condition is false, clear Description the TF flag. This is useful for temporarily storing a condition for later use. if (CNDF == true) TF = 1;...

  • Page 130: Ui16Tof32 Rah, Mem16 Convert Unsigned 16-Bit Integer To 32-Bit Floating-Point Value

    Instructions www.ti.com UI16TOF32 RaH, mem16 Convert unsigned 16-bit integer to 32-bit floating-point value Operands floating-point destination register (R0H to R7H) mem16 pointer to 16-bit source memory location Opcode LSW: 1110 0010 1100 0100 MSW: 0000 0aaa mem16 When converting F32 to I16/UI16 data format, the F32TOI16/UI16 operation truncates to Description zero while the F32TOI16R/UI16R operation will round to nearest (even) value.

  • Page 131: Ui16Tof32 Rah, Rbh Convert Unsigned 16-Bit Integer To 32-Bit Floating-Point Value

    Instructions www.ti.com UI16TOF32 RaH, RbH Convert unsigned 16-bit integer to 32-bit floating-point value Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1000 1111 MSW: 0000 0000 00bb baaa When converting F32 to I16/UI16 data format, the F32TOI16/UI16 operation truncates to Description zero while the F32TOI16R/UI16R operation will round to nearest (even) value.

  • Page 132: Ui32Tof32 Rah, Mem32 Convert Unsigned 32-Bit Integer To 32-Bit Floating-Point Value

    Instructions www.ti.com UI32TOF32 RaH, mem32 Convert Unsigned 32-bit Integer to 32-bit Floating-Point Value Operands floating-point destination register (R0H to R7H) mem32 pointer to 32-bit source memory location Opcode LSW: 1110 0010 1000 0100 MSW: 0000 0aaa mem32 Description RaH = UI32ToF32[mem32] This instruction does not affect any flags: Flags Flag...

  • Page 133: Ui32Tof32 Rah, Rbh Convert Unsigned 32-Bit Integer To 32-Bit Floating-Point Value

    Instructions www.ti.com UI32TOF32 RaH, RbH Convert Unsigned 32-bit Integer to 32-bit Floating-Point Value Operands floating-point destination register (R0H to R7H) floating-point source register (R0H to R7H) Opcode LSW: 1110 0110 1000 1011 MSW: 0000 0000 00bb baaa Description RaH = UI32ToF32 RbH This instruction does not affect any flags: Flags Flag...

  • Page 134: Zero Rah Zero The Floating-Point Register Rah

    Instructions www.ti.com ZERO RaH Zero the Floating-Point Register RaH Operands floating-point register (R0H to R7H) Opcode LSW: 1110 0101 1001 0aaa Zero the indicated floating-point register: Description RaH = 0 This instruction modifies the following flags in the STF register: Flags Flag Modified...

  • Page 135: Zeroa Zero All Floating-Point Registers

    Instructions www.ti.com ZEROA Zero All Floating-Point Registers Operands none Opcode LSW: 1110 0101 0110 0011 Zero all floating-point registers: Description R0H = 0 R1H = 0 R2H = 0 R3H = 0 R4H = 0 R5H = 0 R6H = 0 R7H = 0 This instruction modifies the following flags in the STF register: Flags...
  • Page 136 Instruction Set SPRUEO2A – June 2007 – Revised August 2008 Submit Documentation Feedback...

  • Page 137: Revision History

    Appendix A SPRUEO2A – June 2007 – Revised August 2008 Revision History Changes This revision history lists the technical changes made in the most recent revision. Table A-1. Technical Changes Made in This Revision Location Additions, Deletions, Modifications Figure 1-1 Modified the functional block diagram Section 1.2.1 Added this section.
  • Page 138 Changes www.ti.com Table A-1. Technical Changes Made in This Revision (continued) Location Additions, Deletions, Modifications SUBF32 RdH, ReH, RfH || MOV32 Modified the SUBF32, RdH, ReH, RfH ||MOV32 mem32, RaH instruction mem32, RaH UI16TOF32 RaH, RbH Modified the UI16TOF32 RaH, RbH instruction UI32TOF32 RaH, RbH Modified the UI32TOF32 RaH, RbH instruction Globally...
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