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TMS320C6452 DSP
Texas Instruments TMS320C6452 DSP Manuals
Manuals and User Guides for Texas Instruments TMS320C6452 DSP. We have
2
Texas Instruments TMS320C6452 DSP manuals available for free PDF download: User Manual
Texas Instruments TMS320C6452 DSP User Manual (46 pages)
DSP DDR2 Memory Controller
Brand:
Texas Instruments
| Category:
Controller
| Size: 0.41 MB
Table of Contents
Table of Contents
3
Preface
6
Introduction
9
Purpose of the Peripheral
9
Features
9
Functional Block Diagram
9
Industry Standard(S) Compliance Statement
10
DDR2 Memory Controller Block Diagram
10
Peripheral Architecture
11
Clock Control
11
Memory Map
11
Signal Descriptions
11
DDR2 Memory Controller Signals
12
DDR2 Memory Controller Signal Descriptions
12
Protocol Description(S)
13
DDR2 SDRAM Commands
13
Truth Table for DDR2 SDRAM Commands
13
DDR2 MRS and EMRS Command
14
Refresh Command
15
ACTV Command
15
DCAB Command
16
DEAC Command
16
DDR2 READ Command
17
Memory Width and Byte Alignment
18
DDR2 WRT Command
18
Addressable Memory Ranges
18
Address Mapping
19
Byte Alignment
19
Logical Address-To-DDR2 SDRAM Address Map for 32-Bit SDRAM
19
Bank Configuration Register Fields for Address Mapping
19
Logical Address-To-DDR2 SDRAM Address Map for 16-Bit SDRAM
20
Logical Address-To-DDR2 SDRAM Address Map
21
DDR2 Memory Controller Interface
22
DDR2 SDRAM Column, Row, and Bank Access
22
DDR2 Memory Controller FIFO Description
22
DDR2 Memory Controller FIFO Block Diagram
23
Refresh Scheduling
25
Refresh Urgency Levels
25
Self-Refresh Mode
26
2.10 Reset Considerations
26
DDR2 Memory Controller Reset Block Diagram
26
Reset Sources
26
2.11 DDR2 SDRAM Memory Initialization
27
DDR2 SDRAM Mode Register Configuration
27
DDR2 SDRAM Extended Mode Register 1 Configuration
27
2.12 Interrupt Support
28
2.13 EDMA Event Support
28
2.14 Emulation Considerations
28
Using the DDR2 Memory Controller
29
Connecting the DDR2 Memory Controller to DDR2 SDRAM
29
Connecting to Two 16-Bit DDR2 SDRAM Devices
30
Connecting to a Single 16-Bit DDR2 SDRAM Device
31
Connecting to Two 8-Bit DDR2 SDRAM Devices
32
Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications
33
SDCFG Configuration
33
DDR2 Memory Refresh Specification
34
SDRFC Configuration
34
SDTIM1 Configuration
34
SDTIM2 Configuration
35
DMCCTL Configuration
35
DDR2 Memory Controller Registers
36
Module ID and Revision Register (MIDR)
37
DDR2 Memory Controller Status Register (DMCSTAT)
37
Module ID and Revision Register (MIDR) Field Descriptions
37
DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions
37
SDRAM Configuration Register (SDCFG)
38
SDRAM Configuration Register (SDCFG) Field Descriptions
38
SDRAM Refresh Control Register (SDRFC)
40
SDRAM Refresh Control Register (SDRFC) Field Descriptions
40
SDRAM Timing 1 Register (SDTIM1)
41
SDRAM Timing 1 Register (SDTIM1) Field Descriptions
41
SDRAM Timing 2 Register (SDTIM2)
43
SDRAM Timing 2 Register (SDTIM2) Field Descriptions
43
Burst Priority Register (BPRIO)
44
Burst Priority Register (BPRIO) Field Descriptions
44
DDR2 Memory Controller Control Register (DMCCTL)
45
DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions
45
Important Notice
46
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Texas Instruments TMS320C6452 DSP User Manual (41 pages)
DSP Host Port Interface (HPI)
Brand:
Texas Instruments
| Category:
Recording Equipment
| Size: 0.37 MB
Table of Contents
Table of Contents
3
Preface
6
Introduction
9
Purpose of the Peripheral
9
Features
9
Functional Block Diagram
10
Industry Standard(S) Compliance Statement
11
Terminology Used in this Document
11
HPI Block Diagram
11
Peripheral Architecture
12
Clock Control
12
Memory Map
12
Signal Descriptions
12
Pin Multiplexing
12
Protocol Description
12
Endianness Considerations
12
HPI Pins
13
Architecture and Operation
14
Example of Host-Processor Signal Connections
15
HPI Strobe and Select Logic
16
Options for Connecting Host and HPI Data Strobe Pins
17
Access Types Selectable with the HCNTL Signals
17
Cycle Types Selectable with the HCNTL and HR/W Signals
18
Bit Multiplexed-Mode Host Read Cycle
19
Bit Multiplexed-Mode Host Write Cycle
20
Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write)
21
HRDY Behavior During an HPIC or HPIA Read Cycle in the 16-Bit Multiplexed Mode
22
HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write Cycle Followed by Nonauto-Increment HPID Read Cycle)
22
HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 2: HPIA Write Cycle Followed by Auto-Increment HPID Read Cycles)
23
HRDY Behavior During an HPIC Write Cycle in the 16-Bit Multiplexed Mode
23
HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode (Case 1: no Auto-Incrementing)
24
HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode
24
HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode (Case 2: Auto-Incrementing Selected, FIFO Empty before Write)
24
HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode (Case 3: Auto-Incrementing Selected, FIFO Not Empty before Write)
24
HRDY Behavior During an HPIC or HPIA Read Cycle in the 32-Bit Multiplexed Mode
25
HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write Cycle Followed by Non-Auto-Increment HPID Read Cycle)
25
HRDY Behavior During a Data Read Operation in the 32-Bit Multiplexed Mode
26
HRDY Behavior During an HPIC Write Cycle in the 32-Bit Multiplexed Mode
26
HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 1: no Auto-Incrementing)
27
HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode
27
HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 2: Auto-Incrementing Selected, FIFO Empty before Write)
27
HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 3: Auto-Incrementing Selected, FIFO Not Empty before Write)
28
Fifos in the HPI
29
Reset Considerations
31
Initialization
32
2.10 Interrupt Support
32
Host-To-CPU Interrupt State Diagram
32
CPU-To-Host Interrupt State Diagram
33
2.11 EDMA Event Support
34
2.12 Power Management
34
2.13 Emulation Considerations
34
Registers
35
Peripheral Identification Register (PID)
35
HPI Registers Relative to Base Address 0200 0030H
35
Peripheral Identification Register (PID) Field Descriptions
35
Power and Emulation Management Register (PWREMU_MGMT)
36
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions
36
Host Port Interface Control Register (HPIC)
37
Host Port Interface Control Register (HPIC) - Owner (Host) Access Permissions
37
Host Port Interface Control Register (HPIC)-Non-Owner (DSP) Access Permissions
37
Host Port Interface Control Register (HPIC) Field Descriptions
38
Host Port Interface Write Address Register (HPIAW)
39
Host Port Interface Write Address Register (HPIAW) Field Descriptions
39
Host Port Interface Read Address Register (HPIAR)
40
Host Port Interface Read Address Register (HPIAR) Field Descriptions
40
Important Notice
41
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