Power/Sleep Controller; Power And Reset Domains; Power And Clock Domains - Texas Instruments TMS320C6457 User Manual

Dsp power/sleep controller (psc)
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2

Power/Sleep Controller

2.1

Power and Reset Domains

The C6457 device comprises several power domains to enable minimizing power dissipation for unused
logic on the device. The GPSC is used to control sleep for memories within each power domain.
Additionally, clock gating to each of the logic blocks is managed by the LPSCs of each module. For
modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to
enable and disable that module's clock(s) at the source. For modules that share a clock with other
modules, the LPSC controls the clock gating.
Figure 1
shows the PSC components and the power and clock domains they control. Many modules
reside in the AlwaysOn domain, that always has power and clocks provided. These consist primarily of the
infrastructure components that are responsible for the clock and reset control (PLL Controller, PSC), the
switch fabric that connects all of the modules, and small modules that do not need dynamic enable/disable
because they do not consume a significant amount of power.
Chip
Configuration
Module
Main.PLLC
sysclk1_po
sysclk2_po
sysclkn_po
chip_1_rst_po_n
chip_0_rst_po_n
chip_0_early_rst_po_n
DDR
EMAC
EMIF
McBSP0
McBSP1
Timer0
Timer1
GPIO
I2C
SCRs, bridges and
other non-power
managed modules
DDR.PLLC
SPRUGL4 – March 2009
Submit Documentation Feedback
Figure 1. Power and Clock Domains
Global PSC
rail_gnt_A
iso_ctl_A
rail_gnt_B
iso_ctl_B
rail_gnt_C
iso_ctl_C
rail_gnt_D
iso_ctl_D
sysclkn_pi
chip_0_early_rst_pi_n
por_pi_n
LPSC0
sysclkn
LPSC1
chip_1_rst_po_n
chip_0_rst_po_n
chip_0_early_rst_po_n
LPSC2
LPSC3
LPSC4
LPSC5
(Shared LPSC)
LPSC6
LPSC7
LPSC8
LPSC9
LPSC10
sysclk1_po
sysclk2_po
sysclk3_po
bpsysclk_po
Clock Domain 6
(Never Gated)
AlwaysOn
Power Domain 0
Clock Domain 0
Reserved
Clock Domain 1
C64x+
Clock Domain 2
EMIF64
Clock Domain 3
HPI
Clock Domain 4
UTOPIA
Clock Domain 6
DEBUGSS
Clock Domain 7
SRIO
Clock Domain 8
TCP2_0
Clock Domain 9
TCP2_1
Clock Domain 10
VCP2
TMS320C6457 DSP Power/Sleep Controller (PSC)
Power/Sleep Controller
Proxied
Power Domain 1
SRIO
Proxied
Power Domain 2
TCP2_0
Proxied
Power Domain 3
TCP2_1
Proxied
Power Domain 4
VCP2
7

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