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TMS320C6457
Texas Instruments TMS320C6457 Manuals
Manuals and User Guides for Texas Instruments TMS320C6457. We have
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Texas Instruments TMS320C6457 manuals available for free PDF download: User Manual, Quick Setup Manual
Texas Instruments TMS320C6457 User Manual (79 pages)
DSP Turbo-Decoder Coprocessor 2 (TCP2)
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 0 MB
Table of Contents
Table of Contents
3
Preface
8
Read this First
8
Features
9
Introduction
10
3GPP and IS2000 Turbo-Encoder Block Diagram
10
Overview
11
3GPP and IS2000 Turbo-Decoder Block Diagram
11
Standalone (SA) Mode
12
TCP2 Block Diagram
12
Frame Sizes for Standalone (SA) Mode and Shared-Processing (SP) Mode
12
Input Data Format
13
Standalone (SA) Mode Block Diagram
13
Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and
14
EN = 1 (Little-Endian Mode) Rate
14
EN = 0 (Big-Endian Mode) Rate
14
EN = 0 (Big-Endian Mode) Rate
15
EN = 1 (Little-Endian Mode) Rate
15
Output Decision Data Format
16
Stopping Criteria
16
Rate 3/4 en = 0 (Big-Endian Mode) Rate
16
Interleaver Data
16
Stopping Test Unit
17
Shared-Processing (SP) Mode
18
Shared-Processing (SP) Mode Block Diagram
19
Subframe Equations
20
Frame Process
20
Input Data Format
22
TCP2 Shared Processing Block Diagram
22
Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and
22
EN = 1 (Little-Endian Mode) Rate
22
EN = 0 (Big-Endian Mode) Rate
22
EN = 1 (Little-Endian Mode) Rate
23
EN = 0 (Big-Endian Mode) Rate
23
Output Data Format
24
EN = 0 (Big-Endian Mode) Rate
24
EN = 1 (Little-Endian Mode) Rate
24
Rate 3/4 en = 0 (Big-Endian Mode) Rate
24
A Priori Data
24
Registers
25
TCP2 Rams
25
Peripheral Identification Register (PID)
27
TCP2 Registers
25
Peripheral Identification Register (PID) Field Descriptions
27
TCP2 Input Configuration Register 0 (TCPIC0)
28
TCP2 Input Configuration Register 0 (TCPIC0) Field Descriptions
28
TCP2 Input Configuration Register 1 (TCPIC1)
29
TCP2 Input Configuration Register 2 (TCPIC2)
29
TCP2 Input Configuration Register 1 (TCPIC1) Field Desccriptions
29
TCP2 Input Configuration Register 2 (TCPIC2) Field Descriptions
29
TCP2 Input Configuration Register 3 (TCPIC3)
30
TCP2 Input Configuration Register 4 (TCPIC4)
31
TCP2 Input Configuration Register 4 (TCPIC4) Field Descriptions
31
TCP2 Input Configuration Register 5 (TCPIC5)
32
Tail Symbols
32
CRC Examples
32
TCP2 Input Configuration Register 6 (TCPIC6)
33
TCP2 Input Configuration Register 5 (TCPIC5) Field Descriptions
32
TCP2 Input Configuration Register 6 (TCPIC6) Field Descriptions
33
TCP2 Input Configuration Register 7 (TCPIC7)
34
TCP2 Input Configuration Register 7 (TCPIC7) Field Descriptions
34
TCP2 Input Configuration Register 8 (TCPIC8)
35
TCP2 Input Configuration Register 8 (TCPIC8) Field Descriptions
35
TCP2 Input Configuration Register 9 (TCPIC9)
36
CP2 Input Configuration Register 9 (TCPIC9)
36
CP2 Input Configuration Register 9 (TCPIC9) Field Descriptions
36
TCP2 Input Configuration Register 10 (TCPIC10)
37
TCP2 Input Configuration Register 11 (TCPIC11)
37
TCP2 Input Configuration Register 10 (TCPIC10) Field Descriptions
37
TCP2 Input Configuration Register 11 (TCPIC11)
38
TCP2 Input Configuration Register 11 (TCPIC11) Field Descriptions
38
TCP2 Input Configuration Register 12 (TCPIC12)
39
TCP2 Input Configuration Register 13 (TCPIC13)
39
TCP2 Input Configuration Register 12 (TCPIC12) Field Descriptions
39
TCP2 Input Configuration Register 13 (TCPIC13) Field Descriptions
39
TCP2 Input Configuration Register 14 (TCPIC14)
40
TCP2 Input Configuration Register 14 (TCPIC14) Field Descriptions
40
TCP2 Input Configuration Register 15 (TCPIC15)
41
Extrinsic Scale Registers
41
TCP2 Output Parameter Register 0 (TCPOUT0)
42
TCP2 Output Parameter Register 1 (TCPOUT1)
42
TCP2 Input Configuration Register 15 (TCPIC15) Field Descriptions
41
TCP2 Output Parameter Register 0 (TCPOUT0) Field Descriptions
42
TCP2 Output Parameter Register 1 (TCPOUT1) Field Descriptions
42
TCP2 Output Parameter Register 2 (TCPOUT2)
43
TCP2 Execution Register (TCPEXE)
43
TCP2 Execution Register (TCPEXE) Field Descriptions
43
TCP2 Endian Register (TCPEND)
44
TCP2 Output Parameter Register 2 (TCPOUT2) Field Descriptions
43
TCP2 Endian Register (TCPEND) Field Descriptions
44
TCP2 Error Register (TCPERR)
45
TCP2 Error Register (TCPERR) Field Descriptions
45
TCP2 Status Register (TCPSTAT)
47
TCP2 Status Register (TCPSTAT) Field Descriptions
47
TCP2 Emulation Register (TCPEMU)
49
TCP2 Emulation Register (TCPEMU) Field Descriptions
49
Data Destination - EDMA3 (Big Endian)
50
Data Destination - Kernel (Little Endian)
50
Data Source - EDMA3 (Big Endian)
50
Data Source - Kernel (Little Endian)
50
Endianness
50
Data Memory for Systematic
50
Data Memory
51
EN = 0 (Big-Endian Mode) Rate = 1/2
51
EN = 0 (Big-Endian Mode) Rate = 1/3
51
EN = 1 (Little-Endian Mode) Rate = 1/2
51
EN = 1 (Little-Endian Mode) Rate = 1/3
51
EN = 1 (Little-Endian Mode) Rate = 1/4
51
EN = 0 (Big-Endian Mode) Rate = 1/4
52
EN = 0 (Big-Endian Mode) Rate = 1/5
52
EN = 1 (Little-Endian Mode) Rate = 3/4
52
EN = 0 (Big-Endian Mode) Rate = 3/4
53
EN = 1 (Little-Endian Mode) Rate = 1/5
52
Destination of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0)
53
Source of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0)
53
Source of Endianness Manager - Trellis Stage Ordering of Hard Decisions in 32-Bit Word
53
Destination of Endianness Manager (OUT_ORDER = 0)
54
Data Destination = EDMA3 en = 0 (Big-Endian Mode)
54
Data Source = Kernel
54
Hard Decisions in DSP Memory
54
Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1)
54
Interleaver Data
55
Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1)
55
TCP_ENDIAN Programming Register
55
TCP_ENDIAN Register
55
Data Destination - Kernel (ENDIAN_INTR = 1)
56
Data Source - EDMA3 (ENDIAN_INTR = 1)
56
Interleaver Indexes in DSP Memory (ENDIAN_INTR = 0)
56
Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1)
56
Data Destination - Kernel (ENDIAN_INTR = 0)
57
Data Source - EDMA3 (ENDIAN_INTR = 0)
57
Extrinsic Data
57
Extrinsic in DSP Memory (ENDIAN_EXTR = 1)
57
Data Destination - EDMA3 (ENDIAN_EXTR = 1)
58
Data Source - Kernel (ENDIAN_EXTR = 1)
58
Architecture
59
Data Destination - EDMA3 (ENDIAN_EXTR = 0)
59
Sub-Block and Sliding Window Segmentation
60
Data Source - Kernel (ENDIAN_EXTR = 0)
59
Extrinsic in DSP Memory (ENDIAN_EXTR = 0)
59
MAP Unit Block Diagram
60
Subframe Segmentation (SP Mode Only)
61
Sliding Windows and Sub-Blocks Segmentation (Example with 5 Sub-Blocks, Frame Length 20730)
61
Examples for NUM_BLOCK, NUM_SUBBLOCK, NUM_SW, and WIN_REL
61
Reliability and Prolog Length Calculation
62
Shared Processing Subframe Segmentation (Example with 5 Subframes)
62
Added Features
63
Example R Formula
63
Programming
64
Valid Re-Encode Symbols Used for Comparison
64
EDMA3 Resources
65
EDMA3 Parameters in Shared Processing (SP) Mode
65
Programming Standalone (SA) Mode
66
Programming Shared-Processing (SP) Mode
70
EDMA3 Parameters in Standalone (SA) Mode
65
EDMA3 Parameters Structure
65
Input Configuration Parameters Settings in Standalone (SA) Mode
70
Output Parameters
74
Events Generation
74
TCP2 Events Generation in Standalone (SA) Mode
74
Input Configuration Parameters Settings in Shared-Processing (SP) Mode
74
Debug Mode: Pause after each Map
75
Errors and Status
75
13.1 Errors
75
TCP2 Events Generation in Shared-Processing (SP) Mode
75
13.2 Status
77
Important Notice
79
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Texas Instruments TMS320C6457 User Manual (43 pages)
DSP Host Port Interface (HPI)
Brand:
Texas Instruments
| Category:
Host Adapter
| Size: 0 MB
Table of Contents
Table of Contents
3
About this Manual
6
Notational Conventions
6
Preface
6
Read this First
6
Related Documentation from Texas Instruments
6
Host Port Interface (HPI)
7
HPI Position in the Host-DSP System
7
Summary of the HPI Registers
8
Summary of the HPI Signals
9
Introduction to the HPI
7
HPI Signals
9
Summary of HPI Registers
9
Using the Address Registers
11
Single-HPIA Mode
11
Dual-HPIA Mode
11
Example of Host-DSP Signal Connections When Using the HAS Signal in the 32-Bit Multiplexed Mode
12
HPI Operation
12
Host-HPI Signal Connections
12
Example of Host-DSP Signal Connections When the HAS Signal Is Tied High in the 32-Bit Multiplexed Mode
13
Example of Host-DSP Signal Connections When Using the HAS Signal in the 16-Bit Multiplexed Mode
13
HPI Configuration and Data Flow
14
Example of Host-DSP Signal Connections When the HAS Signal Is Tied High in the 16-Bit Multiplexed Mode
14
HDS2, HDS1, and HCS: Data Strobing and Chip Selection
15
HPI Strobe and Select Logic
15
Options for Connecting Host and HPI Data Strobe Pins
15
HCNTL[1:0] and HR/W: Indicating the Cycle Type
16
Access Types Selectable by the HCNTL Signals
16
Cycle Types Selectable with the HCNTL and HR/W Signals
16
HHWIL: Identifying the First and Second Halfwords in 16-Bit Multiplexed Mode
17
HAS: Forcing the HPI to Latch Control Information Early
17
Bit Multiplexed Mode Host Read Cycle Using HAS
18
Bit Multiplexed Mode Host Write Cycle Using HAS
19
Performing a Multiplexed Access Without HAS
20
Bit Multiplexed Mode Host Read Cycle with HAS Tied High
20
Bit Multiplexed Mode Host Write Cycle with HAS Tied High
21
Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode
22
Hardware Handshaking Using the HPI-Ready (HRDY) Signal
22
Bit Multiplexed Mode Single-Halfword HPIC Cycle with HAS Tied High
22
HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode
23
HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 2: HPIA Write Cycle Followed by Autoincrement HPID Read Cycles)
23
HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle)
23
HRDY Behavior During an HPIC or HPIA Read Cycle in the 16-Bit Multiplexed Mode
23
HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode
24
HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode(Case 2: Autoincrementing Selected, FIFO Empty before Write)
24
HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode (Case 1: no Autoincrementing)
24
HRDY Behavior During an HPIC Write Cycle in the 16-Bit Multiplexed Mode
24
HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode(Case 3: Autoincrementing Selected, FIFO Not Empty before Write)
25
HRDY Behavior During an HPIC or HPIA Read Cycle in the 32-Bit Multiplexed Mode
25
HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle)
26
HRDY Behavior During a Data Read Operation in the 32-Bit Multiplexed Mode (Case 2: HPIA Write Cycle Followed by Autoincrement HPID Read Cycles)
26
HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 1: no Autoincrementing)
27
HRDY Behavior During an HPIC Write Cycle in the 32-Bit Multiplexed Mode
27
HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 2: Autoincrementing Selected, FIFO Empty before Write)
28
HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 3: Autoincrementing Selected, FIFO Not Empty before Write)
28
Software Handshaking Using the HPI Ready (HRDY) Bit
29
Polling the HRDY Bit
29
Host-To-CPU Interrupt State Diagram
30
Interrupts between the Host and the CPU
30
DSPINT Bit: Host-To-CPU Interrupts
30
HINT Bit: CPU-To-Host Interrupts
30
CPU-To-Host Interrupt State Diagram
31
Fifos and Bursting
32
Read Bursting
32
Fifos in the HPI
32
Write Bursting
33
FIFO Flush Conditions
34
FIFO Behavior When a Hardware Reset or Software Reset Occurs
34
Emulation and Reset Considerations
35
Emulation Modes
35
Software Reset Considerations
35
Hardware Reset Considerations
35
Host Port Interface (HPI) Registers
36
Power and Emulation Management Register (PWREMU_MGMT)
37
HPI Registers
36
Introduction
36
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions
37
Host Port Interface Control Register (HPIC)
38
CPU Access Permissions
38
Host Access Permissions
38
Host Port Interface Control Register (HPIC) Field Descriptions
38
Host Port Interface Address Registers (HPIAW and HPIAR)
40
Format of an Address Register (HPIAW or HPIAR) - CPU Access Permissions
40
Format of an Address Register (HPIAW or HPIAR) - Host Access Permissions
40
Host Port Interface Address Registers (HPIAW or HPIAR) Field Descriptions
40
Data Register (HPID)
41
Data Register (HPID) (Host Access Permissions, CPU Cannot Access HPID)
41
Data Register (HPID) Field Descriptions
41
Appendix A Revision History
42
TMS320C6457 HPI Revision History
42
Important Notice
43
Texas Instruments TMS320C6457 User Manual (19 pages)
DSP Power/Sleep Controller (PSC)
Brand:
Texas Instruments
| Category:
Controller
| Size: 0 MB
Table of Contents
Table of Contents
3
Preface
5
Introduction/Feature Overview
6
Purpose of the Peripheral
6
Features
6
Terms and Abbreviations
6
Power/Sleep Controller
7
Power and Reset Domains
7
Power and Clock Domains
7
Power Domain and Module States Defined
8
Power Domain States
8
C6457 Power Domains
8
C6457 Clock Domains
8
Module States
9
Local Reset
9
Executing State Transitions
9
Power Domain State Transitions
9
Module State Transitions
10
Concurrent Power Domain/Module State Transitions
10
Recommendations for Power Domain/Module Sequencing
11
Emulation Support in the PSC
11
PSC Registers
12
Power and Sleep Controller (PSC) Register Map
12
PSC Register Memory Map
12
Register Descriptions
13
Peripheral Identification Register (PID)
13
Peripheral Identification Register (PID) Field Descriptions
13
Power Domain Transition Command Register (PTCMD)
14
Power Domain Transition Command Register (PTCMD) Field Descriptions
14
Power Domain Transition Status Register (PTSTAT)
15
Power Domain Status Register 0-4 (Pdstatx)
15
Power Domain Transition Status Register (PTSTAT) Field Descriptions
15
Power Domain Status Register 0-4 (Pdstatx) Field Descriptions
15
Power Domain Control Register 0-4 (Pdctlx)
16
Power Domain Control Register 0-4 (Pdctlx) Field Descriptions
16
Module Status Register 0-10 (Mdstaty)
17
Module Status Register 0-10 (Mdstaty) Field Descriptions
17
Module Control Register 0-10 (Mdctly)
18
Module Control Register 0-10 (Mdctly) Field Descriptions
18
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Texas Instruments TMS320C6457 Quick Setup Manual (2 pages)
Lite Evaluation Module
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 5 MB
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