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Texas Instruments TMS320C6747 DSP User Manual

Texas Instruments TMS320C6747 DSP User Manual

Processor universal serial bus (usb1.1) ohci host controller
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Download this manual See also: Reference Manual
TMS320C674x/OMAP-L1x Processor
Universal Serial Bus (USB1.1)
OHCI Host Controller
User's Guide
Literature Number: SPRUFM8
June 2009

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Summary of Contents for Texas Instruments TMS320C6747 DSP

  • Page 1 TMS320C674x/OMAP-L1x Processor Universal Serial Bus (USB1.1) OHCI Host Controller User's Guide Literature Number: SPRUFM8 June 2009...
  • Page 2 SPRUFM8 – June 2009 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Preface Introduction Purpose of the Peripheral Architecture Clock and Reset Open Host Controller Interface Functionality Differences From OHCI Specification for USB Implementation of OHCI Specification for USB1.1 OHCI Interrupts USB1.1 Host Controller Access to System Memory Physical Addressing Registers OHCI Revision Number Register (HCREVISION) HC Operating Mode Register (HCCONTROL) HC Command and Status Register (HCCOMMANDSTATUS) HC Interrupt and Status Register (HCINTERRUPTSTATUS)
  • Page 4 Relationships Between Virtual Address Physical Address OHCI Revision Number Register (HCREVISION) HC Operating Mode Register (HCCONTROL) HC Command and Status Register (HCCOMMANDSTATUS) HC Interrupt and Status Register (HCINTERRUPTSTATUS) HC Interrupt Enable Register (HCINTERRUPTENABLE) HC Interrupt Disable Register (HCINTERRUPTDISABLE) HC HCAA Address Register (HCHCCA) HC Current Periodic Register (HCPERIODCURRENTED) HC Head Control Register (HCCONTROLHEADED) HC Current Control Register (HCCONTROLCURRENTED)
  • Page 5 www.ti.com USB1.1 Host Controller Registers OHCI Revision Number Register (HCREVISION) Field Descriptions HC Operating Mode Register (HCCONTROL) Field Descriptions HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions HC HCAA Address Register (HCHCCA) Field Descriptions HC Current Periodic Register (HCPERIODCURRENTED) Field Descriptions...

  • Page 6: Preface

    A legend explains the notation used for the properties. – Reserved bits in a register figure designate a bit that is used for future device expansion. Related Documentation From Texas Instruments The following documents describe the TMS320C674x Digital Signal Processors (DSPs) and OMAP-L1x Applications Processors.
  • Page 7 CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory. SPRUFM8 – June 2009 Submit Documentation Feedback Related Documentation From Texas Instruments Read This First...

  • Page 8: Introduction

    Universal Serial Bus OHCI Host Controller Introduction This document describes the universal serial bus OHCI host controller. Purpose of the Peripheral The USB1.1 OHCI host controller (HC) is a single port controller that communicates with USB devices at the USB low-speed (1.5M bit-per-second maximum) and full-speed (12M bit-per-second maximum) data rates.

  • Page 9: Architecture

    www.ti.com Architecture Clock and Reset The USB1.1 module requires that several different clocks are present before it can be accessed: 1. Internal system bus clocks for accesses by the ARM or DSP (Device SYSCLK2 and SYSCLK4) 2. Local bus clock to the USB1.1 host controller (derived from SYSCLK4) 3.

  • Page 10: Open Host Controller Interface Functionality

    Architecture Open Host Controller Interface Functionality 2.2.1 OHCI Controller Overview The Open HCI—Open Host Controller Interface Specification for USB, Release 1.0a defines a set of registers and data structures stored in system memory that control how a USB host controller interfaces to system software.

  • Page 11: Implementation Of Ohci Specification For Usb1.1

    www.ti.com Implementation of OHCI Specification for USB1.1 2.4.1 USB1.1 Host Controller Endpoint Descriptor (ED) List Head Pointers The OHCI Specification for USB provides a specific sequence of operations for the host controller driver to perform when setting up the host controller. Failure to follow that sequence can result in malfunction. As a specific example, the HCCONTROLHEADED and HCBULKHEADED pointer registers and the 32 HCCAINTERRUPTTABLE pointers must all point to valid physical addresses of valid endpoint descriptors.

  • Page 12: Ohci Interrupts

    Architecture OHCI Interrupts The USB1.1 host controller is controlled by either the ARM or the DSP. It has the ability to interrupt either processor. USB1.1 Host Controller Access to System Memory The USB1.1 module needs to access system memory to read and write the OHCI data structures and data buffers associated with USB traffic.

  • Page 13: Registers

    www.ti.com Registers Most of the host controller (HC) registers are OHCI operational registers, defined by the OHCI Specification for USB. Four additional registers not specified by the OHCI Specification for USB provide additional information about the USB1.1 host controller state. The USB1.1 host controller registers can be accessed in user and supervisor modes.

  • Page 14: Ohci Revision Number Register (Hcrevision)

    Registers OHCI Revision Number Register (HCREVISION) The OHCI revision number register (HCREVISION) is shown in Figure 2. OHCI Revision Number Register (HCREVISION) Reserved LEGEND: R = Read only; -n = value after reset Table 2. OHCI Revision Number Register (HCREVISION) Field Descriptions Field Value Description...

  • Page 15: Hc Operating Mode Register (Hccontrol) Field Descriptions

    www.ti.com Table 3. HC Operating Mode Register (HCCONTROL) Field Descriptions Field Value Description 31-11 Reserved Reserved Remote wake-up enable. Remote wake-up connected. Interrupt routing. The USB1.1 host controller does not provide an SMI interrupt. This bit must be 0 to allow the USB1.1 host controller interrupt to propagate to the MPU level 2 interrupt controller.

  • Page 16: Hc Command And Status Register (Hccommandstatus)

    Registers HC Command and Status Register (HCCOMMANDSTATUS) The HC command and status register (HCCOMMANDSTATUS) shows the current state of the host controller and accepts commands from the host controller driver. HCCOMMANDSTATUS is shown in Figure 4 and described in Table Figure 4.

  • Page 17: Hc Interrupt And Status Register (Hcinterruptstatus)

    www.ti.com HC Interrupt and Status Register (HCINTERRUPTSTATUS) The HC interrupt and status register (HCINTERRUPTSTATUS) reports the status of the USB1.1 host controller internal interrupt sources. HCINTERRUPTSTATUS is shown in Table Figure 5. HC Interrupt and Status Register (HCINTERRUPTSTATUS) Rsvd Reserved LEGEND: R/W = Read/Write;...

  • Page 18: Hc Interrupt Enable Register (Hcinterruptenable)

    Registers HC Interrupt Enable Register (HCINTERRUPTENABLE) The HC interrupt enable register (HCINTERRUPTENABLE) enables various OHCI interrupt sources to generate interrupts to the level 2 interrupt controller. HCINTERRUPTENABLE is shown in described in Table Figure 6. HC Interrupt Enable Register (HCINTERRUPTENABLE) R/W1S-0 Reserved LEGEND: R/W = Read/Write;...

  • Page 19: Hc Interrupt Disable Register (Hcinterruptdisable)

    www.ti.com HC Interrupt Disable Register (HCINTERRUPTDISABLE) The HC interrupt disable register (HCINTERRUPTDISABLE) is used to clear bits in the HC interrupt enable register (HCINTERRUPTENABLE). HCINTERRUPTDISABLE is shown in Table Figure 7. HC Interrupt Disable Register (HCINTERRUPTDISABLE) R/W-0 Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7.

  • Page 20: Hc Hcaa Address Register (Hchcca)

    Registers HC HCAA Address Register (HCHCCA) The HC HCAA address register (HCHCCA) defines the physical address of the beginning of the HCCA. HCHCCA is shown in Figure 8 Figure 8. HC HCAA Address Register (HCHCCA) HCCA R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8.

  • Page 21: Hc Head Control Register (Hccontrolheaded)

    www.ti.com HC Head Control Register (HCCONTROLHEADED) The HC head control register (HCCONTROLHEADED) defines the physical address of the head endpoint descriptor (ED) on the control ED list. HCCONTROLHEADED is shown in Table Figure 10. HC Head Control Register (HCCONTROLHEADED) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 10.

  • Page 22: Hc Current Control Register (Hccontrolcurrented)

    Registers 3.10 HC Current Control Register (HCCONTROLCURRENTED) The HC current control register (HCCONTROLCURRENTED) defines the physical address of the next endpoint descriptor (ED) on the control ED list. HCCONTROLCURRENTED is shown in described in Table Figure 11. HC Current Control Register (HCCONTROLCURRENTED) LEGEND: R/W = Read/Write;...

  • Page 23: Hc Head Bulk Register (Hcbulkheaded)

    www.ti.com 3.11 HC Head Bulk Register (HCBULKHEADED) The HC head bulk register (HCBULKHEADED) defines the physical address of the head endpoint descriptor (ED) on the bulk ED list. HCBULKHEADED is shown in Figure 12. HC Head Bulk Register (HCBULKHEADED) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 12.

  • Page 24: Hc Head Done Register (Hcdonehead)

    Registers 3.13 HC Head Done Register (HCDONEHEAD) The HC head done register (HCDONEHEAD) defines the physical address of the current head of the done TD queue. HCDONEHEAD is shown in Figure 14. HC Head Done Register (HCDONEHEAD) LEGEND: R = Read only; -n = value after reset Table 14.

  • Page 25: Hc Frame Remaining Register (Hcfmremaining)

    www.ti.com 3.15 HC Frame Remaining Register (HCFMREMAINING) The HC frame remaining register (HCFMREMAINING) reports the number of full-speed bit times remaining in the current frame. HCFMREMAINING is shown in Figure 16. HC Frame Remaining Register (HCFMREMAINING) Reserved LEGEND: R = Read only; -n = value after reset Table 16.

  • Page 26: Hc Periodic Start Register (Hcperiodicstart)

    Registers 3.17 HC Periodic Start Register (HCPERIODICSTART) The HC periodic start register (HCPERIODICSTART) defines the position within the USB frame where endpoint descriptors (EDs) on the periodic list have priority over EDs on the bulk and control lists. HCPERIODICSTART is shown in Figure 18.

  • Page 27: Hc Low-Speed Threshold Register (Hclsthreshold)

    www.ti.com 3.18 HC Low-Speed Threshold Register (HCLSTHRESHOLD) The HC low-speed threshold register (HCLSTHRESHOLD) defines the latest time in a frame that the USB1.1 host controller can begin a low-speed packet. HCLSTHRESHOLD is shown in described in Table Figure 19. HC Low-Speed Threshold Register (HCLSTHRESHOLD) Reserved LEGEND: R/W = Read/Write;...

  • Page 28: Hc Root Hub A Register (Hcrhdescriptora)

    Registers 3.19 HC Root Hub A Register (HCRHDESCRIPTORA) The HC root hub A register (HCRHDESCRIPTORA) defines several aspects of the USB1.1 host controller root hub functionality. HCRHDESCRIPTORA is shown in Figure 20. HC Root Hub A Register (HCRHDESCRIPTORA) POTPG R/W-Ah Reserved NOCP OCPM R/W-1...

  • Page 29: Hc Root Hub B Register (Hcrhdescriptorb)

    www.ti.com 3.20 HC Root Hub B Register (HCRHDESCRIPTORB) The HC root hub B register (HCRHDESCRIPTORB) defines several aspects of the USB1.1 host controller root hub functionality. HCRHDESCRIPTORB is shown in Note: The device does not provide connections from the USB1.1 host controller to pins to provide external port power switching.

  • Page 30: Hc Root Hub Status Register (Hcrhstatus)

    Registers 3.21 HC Root Hub Status Register (HCRHSTATUS) The HC root hub status register (HCRHSTATUS) reports the USB1.1 host controller root hub status. HCRHSTATUS is shown in Figure 22 Figure 22. HC Root Hub Status Register (HCRHSTATUS) CRWE R/W-0 DRWE R/W-0 LEGEND: R/W = Read/Write;...

  • Page 31: Hc Port 1 Status And Control Register (Hcrhportstatus1)

    www.ti.com 3.22 HC Port 1 Status and Control Register (HCRHPORTSTATUS1) The HC port 1 status and control register (HCRHPORTSTATUS1) reports and controls the state of USB1.1 host port 1. HCRHPORTSTATUS1 is shown in Figure 23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Reserved LEGEND: R/W = Read/Write;...
  • Page 32 Registers Table 23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions (continued) Field Value Description PPS/SPP Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set the port 1 port power status bit; a write of 0 has no effect. The device does not provide signals from the USB1.1 host controller to control external port power, so if required, USB1.1 host port power control signals must be controlled through other means.

  • Page 33: Hc Port 2 Status And Control Register (Hcrhportstatus2)

    www.ti.com 3.23 HC Port 2 Status and Control Register (HCRHPORTSTATUS2) The HC port 2 status and control register (HCRHPORTSTATUS2) reports and controls the state of USB1.1 host port 2. HCRHPORTSTATUS2 is shown in Figure 24. HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Reserved LEGEND: R/W = Read/Write;...
  • Page 34 Registers Table 24. HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions (continued) Field Value Description PPS/SPP Port 2 port power status/set port power. This bit indicates, when read as 1, that the port 2 power is enabled. When read as 0, port 2 power is not enabled. The device does not provide signals from the USB1.1 host controller to control external port power, so, if required, USB1.1 host port power control signals must be controlled through other means.

  • Page 35: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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