Psc Registers; Power And Sleep Controller (Psc) Register Map; Psc Register Memory Map - Texas Instruments TMS320C6457 User Manual

PSC Registers

3 PSC Registers
This section includes the PSC memory map and bit registers.
3.1

Power and Sleep Controller (PSC) Register Map

This section includes the PSC memory map and bit registers.
map.
Offset
0x0
0x014
0x120
0x128
0x200
0x300
0x304
0x308
0x30C
0x310
0x800
0x804
0x808
0x80C
0x810
0x814
0x818
0x81C
0x820
0x824
0x828
0xA00
0xA04
0xA08
0xA0C
0xA10
0xA14
0xA18
0xA1C
0xA20
0xA24
0xA28
12 TMS320C6457 DSP Power/Sleep Controller (PSC)
Table 4. PSC Register Memory Map
Register Description
PID Peripheral Revision and Class Information
- Reserved
PTCMD Power Domain Transition Command Register
PTSTAT Power Domain Transition Status Register
PDSTATx Power Domain Status Register 0-5
PDCTL0 Power Domain Control Register 0 (AlwaysOn)
PDCTL1 Power Domain Control Register 1 (Serial RapidIO)
PDCTL2 Power Domain Control Register 2 (TCP2_0)
PDCTL3 Power Domain Control Register 3 (TCP2_1)
PDCTL4 Power Domain Control Register 4 (VCP2)
MDSTAT0 Module Status Register 0 (Reserved)
MDSTAT1 Module Status Register 1 (C64x+ Core)
MDSTAT2 Module Status Register 2 (EMIF64)
MDSTAT3 Module Status Register 3 (HPI)
MDSTAT4 Module Status Register 4 (UTOPIA)
MDSTAT5 Module Status Register 5 (Never Gated)
MDSTAT6 Module Status Register 6 (DEBUGSS)
MDSTAT7 Module Status Register 7 (Serial RapidIO)
MDSTAT8 Module Status Register 8 (TCP2_0)
MDSTAT9 Module Status Register 9 (TCP2_1)
MDSTAT10 Module Status Register 10 (VCP2)
MDCTL0 Module Control Register 0 (Reserved)
MDCTL1 Module Control Register 1 (C64x+ Core)
MDCTL2 Module Control Register 2 (EMIF64)
MDCTL3 Module Control Register 3 (HPI)
MDCTL4 Module Control Register 4 (UTOPIA)
MDCTL5 Module Control Register 5 (Never Gated)
MDCTL6 Module Control Register 6 (DEBUGSS)
MDCTL7 Module Control Register 7 (Serial RapidIO)
MDCTL8 Module Control Register 8 (TCP2_0)
MDCTL9 Module Control Register 9 (TCP2_1)
MDCTL10 Module Control Register 10 (VCP2)
Table 4 provides the PSC register memory
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See
Section 3.2.1
Section 3.2.2
Section 3.2.3
Section 3.2.4
Section 3.2.5
Section 3.2.5
Section 3.2.5
Section 3.2.5
Section 3.2.5
Section 3.2.6
Section 3.2.6
Section 3.2.6
Section 3.2.6
Section 3.2.6
Section 3.2.6
Section 3.2.6
Section 3.2.6
Section 3.2.6
Section 3.2.6
Section 3.2.6
Section 3.2.7
Section 3.2.7
Section 3.2.7
Section 3.2.7
Section 3.2.7
Section 3.2.7
Section 3.2.7
Section 3.2.7
Section 3.2.7
Section 3.2.7
Section 3.2.7
SPRUGL4 – March 2009