Switches - Xilinx KCU105 User Manual

Table 1-22 shows the level-shifter U40 and U41 connections to FPGA U1.
Table 1-22: PMOD Connector J52, J53 Connections via Level-shifter U42, U43 to FPGA U1
FPGA Schematic Net
(U1) Pin Name
AM25 PMOD0_0_LS
AN21 PMOD0_1_LS
AH18 PMOD0_2_LS
AM19 PMOD0_3_LS
AE26 PMOD0_4_LS
AD24 PMOD0_5_LS
AE21 PMOD0_6_LS
AM17 PMOD0_7_LS
AL14 PMOD1_0_LS
AM14 PMOD1_1_LS
AP16 PMOD1_2_LS
AP15 PMOD1_3_LS
AM16 PMOD1_4_LS
AM15 PMOD1_5_LS
AN18 PMOD1_6_LS
AN17 PMOD1_7_LS
For more information about PMOD connector compatible PMOD modules, see

Switches

[Figure 1-2, callouts 27, 30]
The KCU105 evaluation board includes a power on-off slide switch and a configuration
pushbutton switch:
• Power On/Off Slide Switch SW1 (callout 30)
• FPGA PROG_B SW4, active-Low (callout 27)
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
FPGA (U1)
I/O Standard
Direction
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
I/O LVCMOS12
www.xilinx.com
Chapter 1: KCU105 Evaluation Board Features
Level-Shifter
Side A 1.2V Side B 3.3V
U41.1 U41.20
U41.3 U41.18
U41.4 U41.17
U41.5 U41.16
U41.6 U41.15
U41.7 U41.14
U41.8 U41.13
U41.9 U41.12
U42.1 U42.20
U42.3 U42.18
U42.4 U42.17
U42.5 U42.16
U42.6 U42.15
U42.7 U42.14
U42.8 U42.13
U42.9 U42.12
PMOD
Schematic
Conn.
Net Name
Pin
PMOD0_0 J52.1
PMOD0_1 J52.3
PMOD0_2 J52.5
PMOD0_3 J52.7
PMOD0_4 J52.2
PMOD0_5 J52.4
PMOD0_6 J52.6
PMOD0_7 J52.8
PMOD1_0 J53.1
PMOD1_1 J53.3
PMOD1_2 J53.5
PMOD1_3 J53.7
PMOD1_4 J53.2
PMOD1_5 J53.4
PMOD1_6 J53.6
PMOD1_7 J53.8
[Ref 27].
66
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