Xilinx KCU105 User Manual page 29

Table 1-7 lists the source devices for each clock.
Table 1-7: KCU105 Board Clock Sources
Clock Name
System Clock 300 MHz
System Clock 125 MHz
EMC Clock 90 MHz
System Ctlr. Clock
33.333 MHz
User Clock
10MHz-810 MHz
GTH SMA REF Clock
User SMA Clock
Jitter Attenuated Clock
CKOUT1
Jitter Attenuated Clock
CKOUT2
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Chapter 1: KCU105 Evaluation Board Features
Clock Ref. Des.
• Silicon Labs Si5335A 1.8V LVDS Any Frequency Quad
Clock Generator CLK0.
U122
• See Clock Generation
SYSCLK_300_N).
• Silicon Labs Si5335A 1.8V LVDS Any Frequency Quad
Clock Generator CLK1.
U122
• See Clock Generation
• Silicon Labs Si5335A 1.8V LVCMOS Single-Ended Any
Frequency Quad Clock Generator CLK2.
U122
• See Clock Generation
• Silicon Labs Si5335A 1.8V LVCMOS single-ended any
frequency quad clock generator CLK3.
U122
• See Clock Generation
• Silicon Labs Si570 3.3V LVDS I2C programmable
oscillator, 156.250 MHz default. Available from the
output Q0 of Silicon Labs Si53340 clock buffer.
U32
• See Programmable User Clock Source
(USER_SI570_CLOCK_P and USER_SI570_CLOCK_N).
• User clock input SMAs.
J33(P), J32(N)
• See GTH TX and RX SMA Differential Pairs
(SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N).
• User clock input SMAs.
J34(P), J35(N)
• See User SMA Clock Input
USER_SMA_CLOCK_N).
• Silicon Labs Si5328B LVDS precision clock
multiplier/jitter attenuator.
U57
• See Jitter Attenuated Clock
SI5328_OUT_N).
• Silicon Labs Si5328B LVDS precision clock
multiplier/jitter attenuator.
U57
• See Jitter Attenuated Clock
SI5328_OUT2_N).
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Description
(SYSCLK_300_P and
(CLK_125MHZ).
(FPGA_EMCCLK).
(SYSCTLR_CLK).
(USER_SMA_CLOCK_P and
(SI5328_OUT_P and
(SI5328_OUT2_P and
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