Table of Contents
Advertisement
VC709 Evaluation Board Features
Chapter 1:
Table 1-19: GPIO Connections to FPGA U1 (Cont'd)
XCVX690T (U1) Pin
AV30
AY33
BA31
BA32
AW30
AY30
BA30
BB31
Reset Pushbutton Switch
AV40
Switches
[Figure
The VC709 board includes a power and a configuration switch:
•
•
•
FPGA_PROG_B Pushbutton SW9 (Active-Low)
[Figure
Switch SW9 grounds the FPGA PROG_B pin when pressed. This action initiates an FPGA
reconfiguration. The FPGA_PROG_B signal is connected to FPGA U1 pin AJ11.
See 7 Series FPGAs Configuration User Guide (UG470)
the 7 series FPGAs.
Figure 1-21
X-Ref Target - Figure 1-21
52
Send Feedback
Net Name
GPIO_DIP_SW0
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
GPIO_DIP_SW4
GPIO_DIP_SW5
GPIO_DIP_SW6
GPIO_DIP_SW7
CPU_RESET
1-2, callout 19, 20, and 21]
FPGA_PROG_B, active-Low pushbutton switch SW9 (callout 19)
Configuration mode DIP switch SW11 (callout 20)
Power on/off slide switch SW12 (callout 21)
1-2, callout 19]
shows SW9.
FPGA_PROG_B
Figure 1-21: FPGA_PROG_B Pushbutton SW9
www.xilinx.com
I/O Standard
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
[Ref
3]for further details on configuring
VCC1V8
R42
4.7kΩ
0.1 W
5%
SW9
1
4
2
3
GND
UG887_c1_22_090612
UG887 (v1.6) March 11, 2019
GPIO Pin
SW2.16
SW2.15
SW2.14
SW2.13
SW2.12
SW2.11
SW2.10
SW2.9
SW8.3
VC709 Evaluation Board
Advertisement
Table of Contents
