Xilinx KCU105 User Manual page 74

Table 1-23: FMC HPC J22 Connections to XCKU040 Device U1 (Cont'd)
J22
Schematic Net Name
Pin
Notes:
1. Series capacitor coupled to the XCKU040 U1 pin.
2. U30 MAX15301 VADJ_1V8_FPGA voltage regulator power good output signal.
3. XCKU040 U1 JTAG TCK, TMS, TDO pins AC9, W9, U9 buffered by U19 SN74AVC8T245.
4. J22 HPC TDO-TDI connections to U26 HPC FMC JTAG bypass switch (N.C. normally closes/bypassing J22 until an FMC
card is plugged into J22).
5. FMC_HPC_PRSNT_M2C_B is the HPC FMC JTAG bypass switch U26.4 OE control signal and is also connected to the
XCKU040 U1 pin H24 via level-shifter U44.
6. Connected to the XCKU040 U1 LS pins J25/J24 IIC_MAIN_SDA/SCL via I2C MUX U80 and level-shifter U77.
7. HPC FMC signal FMC_HPC_PG_M2C is connected to the XCKU040 U1 pin L27 via level-shifter U44.
FMC LPC Connector J2
[Figure 1-2, callout 34]
The 160-pin LPC connector defined by the FMC specification
connectivity for up to:
• 68 single-ended or 34 differential user-defined signals
• 1 GTH transceiver
• 1 GTH clock
• 2 differential clocks
• 61 ground and 9 power connections
The LPC connector at J2 implements the full FMC LPC connectivity:
• 34 differential user-defined pairs (34 LA pairs, LA00-LA33)
• 1 GTH transceiver
• 1 GTH clock
• 2 differential clocks
• 61 ground and 9 power connections
The FMC DP[7:0] transmit and receive signal data paths are routed with a differential
characteristic impedance of 100Ω (±10%) with an insertion loss of <4 dB up to 8 GHz.
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
I/O
XCKU040
Standard (U1) Pin J22 Pin
K40
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Chapter 1: KCU105 Evaluation Board Features
Schematic Net Name
(Figure B-1, page
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XCKU040
I/O Standard
(U1) Pin
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