Xilinx KCU105 User Manual page 31

System Clock Source
[Figure 1-2, callout 6]
The system clock source is a Silicon Labs Si5335A quad clock generator/buffer at U122. The
system clock (SYSCLK) is a LVDS 300 MHz clock sourced from the CLK0A output pair of
U122. SYSCLK is wired to a clock capable (GC) input on programmable logic bank 45. The
signal pair is named SYSCLK_300_P and SYSCLK_300_N connected to the XCKU040 device
U1 (bank 45 pins AK17 and AK16, respectively).
• Clock Generator: Silicon Labs Si5335A-B03426-GM (CLK0A 300 MHz)
• Low phase jitter of 0.7 pS RMS
• LVDS Differential Output
The system clock circuit is shown in
X-Ref Target - Figure 1-10
Three additional clocks are sourced from the U122 quad clock generator:
• 125 MHz LVDS signal pair CLK_125MHZ_P and CLK_125MHZ_N, connected to the
XCKU040 device U1 bank 66 pins G10 and F10, respectively.
• 90.0 MHz single-ended 1.8V LVCMOS, series resistor coupled FPGA_EMCCLK,
connected to the XCKU040 device U1 bank 65 dedicated EMCCLK input pin K20.
• 33.3333 MHz single-ended 1.8V LVCMOS, series resistor coupled SYSCTLR_CLK,
connected to system controller XC7Z010 Zynq-7000 AP SoC U111 bank 500 dedicated
PS_CLK input pin C7.
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Figure 1-10.
Figure 1-10: KCU105 Board System Clock
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Chapter 1: KCU105 Evaluation Board Features
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