Hdmi Video Output - Xilinx KCU105 User Manual

Table 1-17 lists the CP2105GM connections to FPGA U1.
Table 1-17: FPGA U1 to CP2105GM U34 Connections
FPGA (U1) Pin Function Direction
G25 RX
K26 TX
L23 CTS
K27 RTS
Notes:
1. The USB_UART_sig nets are named from the perspective of the CP2105GM device (U34).
For more technical information on the CP2105GM and the VCP drivers, see the Silicon Labs
website [Ref 28].
Xilinx UART IP is expected to be implemented in the FPGA logic using IP as described in the
LogiCORE IP AXI UART Lite Product Guide (PG142)

HDMI Video Output

[Figure 1-2, callout 20]
The KCU105 evaluation board provides a HDMI video output using an Analog Devices
ADV7511KSTZ-P HDMI transmitter at U52. The HDMI transmitter U52 is connected to the
XCKU040 device bank 64 and its output is provided on a Molex 500254-1927 HDMI type-A
receptacle at P6. The ADV7511 supports 1080P 60 Hz, YCbCr 4:2:2 encoding via 16-bit input
data mapping.
The KCU105 evaluation board supports these HDMI device interfaces:
• 16 data lines
• Independent VSYNC, HSYNC
• Single-ended input CLK
• Interrupt Out Pin to FPGA
• I2C
• SPDIF
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
I/O Standard
XCKU040 FPGA (U1) - UART1 SCI
Input LVCMOS18
Output LVCMOS18
Output LVCMOS18
Input LVCMOS18
www.xilinx.com
Chapter 1: KCU105 Evaluation Board Features
CP2105GM Device (U34)
Schematic Net
Name
Pin
(1)
USB_UART_TX 21
USB_UART_RX 20
USB_UART_CTS 18
USB_UART_RTS 19
[Ref 11].
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Function Direction
TXD Output
RXD Input
CTS Input
RTS Output
52