Xilinx KCU105 User Manual page 20

Table 1-4: DDR4 Memory Connections to the FPGA (Cont'd)
FPGA Schematic Net
(U1) Pin
AN31 DDR4_DQ61
AL34 DDR4_DQ62
AN32 DDR4_DQ63
AH33 DDR4_DQS6_T
AJ33 DDR4_DQS6_C
AN34 DDR4_DQS7_T
AP34 DDR4_DQS7_C
AJ29 DDR4_DM6
AL32 DDR4_DM7
AE17 DDR4_A0
AH17 DDR4_A1
AE18 DDR4_A2
AJ15 DDR4_A3
AG16 DDR4_A4
AL17 DDR4_A5
AK18 DDR4_A6
AG17 DDR4_A7
AF18 DDR4_A8
AH19 DDR4_A9
AF15 DDR4_A10
AD19 DDR4_A11
AJ14 DDR4_A12
AG19 DDR4_A13
AD16 DDR4_A14_WE_B
AG14 DDR4_A15_CAS_B
AF14 DDR4_A16_RAS_B
AF17 DDR4_BA0
AL15 DDR4_BA1
AG15 DDR4_BG0
AH14 DDR4_ACT_B
AH16 DDR4_TEN
AJ16 DDR4_ALERT_B
AD18 DDR4_PAR
AJ18 DDR4_ODT
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
I/O Standard
Name
POD12_DCI
POD12_DCI
POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
POD12_DCI
POD12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
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Chapter 1: KCU105 Evaluation Board Features
Component Memory
Pin # Pin Name
C8 DQU5
D3 DQU6
D7 DQU7
G3 DQSL_T
F3 DQSL_C
B7 DQSU_T
A7 DQSU_C
E7 DML_B/DBIL_B
E2 DMU_B/DBIU_B
P3 A0
P7 A1
R3 A2
N7 A3
N3 A4
P8 A5
P2 A6
R8 A7
R2 A8
R7 A9
M3 A10/AP
T2 A11
M7 A12/BC_B
T8 A13
L2 WE_B/A14
M8 CAS_B/A15
L8 RAS_B/A16
N2 BA0
N8 BA1
M2 BG0
L3 ACT_B
N9 TEN
P9 ALERT_B
T3 PAR
K3 ODT
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Ref. Des.
U63
U63
U63
U63
U63
U63
U63
U63
U63
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
U60-U62
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