Xilinx KCU105 User Manual page 56

The TCA9548 U28 RESET_B pin 3 is connected to FPGA U1 bank 64 pin AP10 via
IMPORTANT:
level-shifter U44. The PCA9544 does not have a reset pin. FPGA pin AP10 LVCMOS18 net
IIC_MUX_RESET_B_LS must be driven High to enable I2C bus transactions with the devices connected to
U28.
User FPGA applications that communicate with devices on one of the downstream I2C
buses must first set up a path to the desired target bus through the U28 or U80 bus switch
at I2C address 0x74 (0b1110100) or 0x75 (0b1110101), respectively.
address for each device on the I2C bus.
Table 1-19: I2C Devices
I2C Devices
TCA9548 8-channel bus switch
Si570 clock
I2C port expander
SFP module 0 (SFP0)
SFP module 1 (SFP1)
Si5328 clock
ADV7511 HDMI
FPGA SYSMON
Not used
PCA9544 4-channel bus switch
PMBUS regulators
FMC HPC
FMC LPC
I2C EEPROM
Notes:
MAX15301: U29,U30,U31; MAX15303: U3,U4,U6,U7,U8,U9,U10.
Information on the TCA9548 and PCA9544 is available on the Texas Instruments website
[Ref 33].
For additional information on the Zynq-7000 AP SoC device I2C controller, see Zynq-7000
All Programmable SoC Overview Data Sheet (DS190)
Programmable SoC Technical Reference Manual (UG585)
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
I2C Switch
Position
Binary Format
N/A
0b1110100
0
0b1011101
1
0b0100001
2
0b1010000
3
0b1010000
4
0b1101000
5
0b0111001
6
0b0110010
7 N/A
N/A
0b1110101
0b0010000-
0
0b0011000
1
0bXXXXX00
2
0bXXXXX00
3
0b1010100
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Chapter 1: KCU105 Evaluation Board Features
I2C Address
Hex Format
0x74
0x5D
0x21
0x50
0x50
0x68
0x39
0x32
N/A
0x75
0x10-0x18
0x##
0x##
0x54
[Ref 2] and Zynq-7000 All
[Ref 13].
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Table 1-19 lists the
Device
U28 TCA9548
U32 Si570
U89 TCA6416
P5 SFP0
P4 SFP1
U57 Si5328B
U52 ADV7511
U1 SYSMON
N/A
U80 PCA9544
MAX15301/3 (1)
J22 FMC HPC
J2 FMC LPC
U12 M24C08
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