Xilinx KCU105 User Manual page 87

The system controller is delivered as a black-box design that communicates with onboard
programmable devices over an I2C interface. The Zynq-7000 AP SoC system controller IP is
not provided and is not available to end users for modification purposes.
The system controller is an ease-of-use feature that sets up or queries onboard resources
available to the XCKU040 UltraScale FPGA U1 on the KCU105 board. Programmable clocks,
the internal UltraScale FPGA system monitor block (SYSMON), and the Maxim power
controllers are accessible through an I2C interface connected to both the system controller
and the FPGA.
A Silicon Labs Si570 programmable low-jitter clock is used to provide a system clock for
FPGA designers. Through a UART (115200-8-N-1) text interface, the system clock (Si570)
can be set to any frequency between 10 MHz and 810 MHz. The Si570 defaults to a
power-on frequency of 156.25 MHz, but then automatically changes to the last saved
frequency setting requested by the user. Clock programming does not require FPGA
resources and can be set or adjusted prior to configuring the FPGA or after the FPGA has
been configured.
Additional functionality provided through the system controller's UART2 is a text display of
the internal SYSMON registers for VCCINT, VCCBRAM, VCCAUX, and the UltraScale FPGA U1
device temperature. SYSMON based power measurements are also displayed over the
UART2 for the VCCINT, VCCBRAM, VCCAUX, VCC1V8, VADJ_1V8, VCC1V2, MGTAVCC, and
MGTAVTT power rails.
Power rail voltages set by the Maxim controllers are also displayed through the UART2 for
VCCINT, VCCBRAM, VCCAUX, VCC1V8, VADJ_1V8, VCC1V2, MGTAVCC, MGTAVTT,
MGTVCCAUX, and UTIL_3V3.
See Appendix C, System Controller
controller text-based UART menu.
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Chapter 1: KCU105 Evaluation Board Features
for information on installing and using the system
www.xilinx.com 87
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