Xilinx KCU105 User Manual page 42

Table 1-11: KCU105 Board FPGA U1 GTH Bank 227 and 228 Connections (Cont'd)
FPGA
Transceiver
(U1) FPGA (U1) Pin Name
Bank
Pin
F6 MGTHTXP0_228
F5 MGTHTXN0_228
E4 MGTHRXP0_228
E3 MGTHRXN0_228
D6 MGTHTXP1_228
D5 MGTHTXN1_228
D2 MGTHRXP1_228
D1 MGTHRXN1_228
C4 MGTHTXP2_228
C3 MGTHTXN2_228
GTH Bank
228
B2 MGTHRXP2_228
B1 MGTHRXN2_228
B6 MGTHTXP3_228
B5 MGTHTXN3_228
A4 MGTHRXP3_228
A3 MGTHRXN3_228
K6 MGTREFCLK0P_228
K5 MGTREFCLK0N_228
H6 MGTREFCLK1P_228
H5 MGTREFCLK1N_228
For additional information on GTH transceivers, see UltraScale Architecture GTH
Transceivers User Guide (UG576)
Guide for Vivado Design Suite (PG182)
FPGA PCIe functionality, see UltraScale Architecture Gen3 Integrated Block for PCI Express
LogiCORE IP Product Guide (PG156)
standard is available at the PCI Express website
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Chapter 1: KCU105 Evaluation Board Features
Schematic Net Name
FMC_HPC_DP0_C2M_P
FMC_HPC_DP0_C2M_N
FMC_HPC_DP0_M2C_P
FMC_HPC_DP0_M2C_N
FMC_HPC_DP1_C2M_P
FMC_HPC_DP1_C2M_N
FMC_HPC_DP1_M2C_P
FMC_HPC_DP1_M2C_N
FMC_HPC_DP2_C2M_P
FMC_HPC_DP2_C2M_N
FMC_HPC_DP2_M2C_P
FMC_HPC_DP2_M2C_N
FMC_HPC_DP3_C2M_P
FMC_HPC_DP3_C2M_N
FMC_HPC_DP3_M2C_P
FMC_HPC_DP3_M2C_N
FMC_HPC_GBTCLK0_M2C_C_P
FMC_HPC_GBTCLK0_M2C_C_N
FMC_HPC_GBTCLK1_M2C_C_P
FMC_HPC_GBTCLK1_M2C_C_N
[Ref 6] and UltraScale FPGAs Transceivers Wizard Product
[Ref 7]. For additional information about UltraScale
[Ref 8]. Additional information about the PCI Express
[Ref 29].
www.xilinx.com
Connected Connected Pin
Pin Name
C2 DP0_C2M_P
C3 DP0_C2M_N
C6 DP0_M2C_P
C7 DP0_M2C_N
A22 DP1_C2M_P
A23 DP1_C2M_N
A2 DP1_M2C_P
A3 DP1_M2C_N
A26 DP2_C2M_P
A27 DP2_C2M_N
A6 DP2_M2C_P
A7 DP2_M2C_N
A30 DP3_C2M_P
A31 DP3_C2M_N
A10 DP3_M2C_P
A11 DP3_M2C_N
D4 GBTCLK0_M2C_P
D5 GBTCLK0_M2C_N
B20 GBTCLK1_M2C_P
B21 GBTCLK1_M2C_N
Send Feedback
Connected
Device
FMC HPC
J22
42