Xilinx KCU105 User Manual page 13

FPGA Configuration
The UltraScale FPGA is configured using either the master SPI or JTAG mode as determined
by the configuration DIP switch SW15.
X-Ref Target - Figure 1-3
Interfaces supporting these configuration modes are:
• Master SPI: Quad SPI flash memory (U35 and U36)
• JTAG:
Digilent USB-to-JTAG configuration module (U115)
°
Platform cable header (J3)
°
System controller (U111)
°
Each configuration interface corresponds to one or more configuration modes and bus
widths, as listed in
1, respectively. FPGA mode pin M2 is wired to SW15 pin 6 position 6, which has a default
setting of OPEN, enabling the M2 net to be pulled down to logic 0 (for example, the FPGA
default mode setting M[2:0] = 001, selecting Quad SPI configuration mode).
Table 1-2: Configuration Modes
Configuration Mode
Master SPI
JTAG
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Figure 1-3: Configuration DIP Switch
Table 1-2. The FPGA mode pins M1 and M0 are hard-wired to logic 0 and
M[2:0] Bus Width
x1, x2, x4
001
x1
101
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Chapter 1: KCU105 Evaluation Board Features
CCLK Direction
Output
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