Xilinx KCU105 User Manual page 63

User SMA GPIO
[Figure 1-2, callout 11]
Figure 1-29 shows the GPIO SMAs J36 and J37.
X-Ref Target - Figure 1-29
Table 1-21 lists the GPIO Connections to FPGA U1.
Table 1-21: KCU105 Board GPIO Connections to FPGA U1
FPGA (U1)
Schematic Net Name
Pin
GPIO LEDs (Active High)
AP8
H23
P20
P21
N22
M22
R23
P23
Directional Pushbuttons (Active High)
AD10
AE8
AF9
AF8
AE10
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Figure 1-29: GPIO SMAs J36 and J37
FPGA (U1)
(1)
GPIO_LED_0
GPIO_LED_1
GPIO_LED_2
GPIO_LED_3
GPIO_LED_4
GPIO_LED_5
GPIO_LED_6
GPIO_LED_7
GPIO_SW_N
GPIO_SW_E
GPIO_SW_W
GPIO_SW_S
GPIO_SW_C
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Chapter 1: KCU105 Evaluation Board Features
I/O Standard
Direction
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Device
DS7.1
DS6.1
DS8.1
DS9.1
DS10.1
DS33.1
DS32.1
DS31.1
SW10.3, U111.A13
SW9.3, U111.B14
SW6.3, U111.D14
SW8.3, U111.C14
SW7.3, U111.B12
63
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