Ultrascale Fpga User Design Considerations - Xilinx KCU105 User Manual

UltraScale FPGA User Design Considerations

The KCU105 system controller provides simplified access to the programmable features on
the KCU105 over an I2C interface. This I2C interface is shared with the UltraScale FPGA and
can be driven by an I2C master within a design.
Access to the I2C devices from either the UltraScale FPGA or the system controller takes
place over the same shared I2C topology. All I2C accesses go through either the TCA9548
8-port I2C switch or the PCA9544 4-port I2C switch. Designs must deassert the TCA9548
reset (signal IIC_MUX_RESET_B) to access any I2C device attached to one of its eight ports.
The PCA9544 4-port I2C switch does not have a reset function.
The TCA9548 U28 RESET_B pin 3 is connected to FPGA U1 bank 64 pin AP10 via
IMPORTANT:
level-shifter U44. The PCA9544 U80 does not have a reset pin. FPGA pin AP10 LVCMOS18 net
IIC_MUX_RESET_B_LS must be driven High to enable I2C bus transactions with the devices connected to
U28.
Designs that access the SYSMON block over I2C must enable the SYSMON I2C interface and
the desired SYSMON channels. See UltraScale Architecture System Monitor User Guide
(UG580) [Ref 12]
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
for designing with the SYSMON block.
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Appendix C: System Controller
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