Xilinx KCU105 User Manual page 41

Table 1-11 lists the GTH banks 227 and 228 interface connections between FPGA U1 and the
FMC HPC J22 connector.
Table 1-11: KCU105 Board FPGA U1 GTH Bank 227 and 228 Connections
FPGA
Transceiver
(U1) FPGA (U1) Pin Name
Bank
Pin
N4 MGTHTXP0_227
N3 MGTHTXN0_227
M2 MGTHRXP0_227
M1 MGTHRXN0_227
L4 MGTHTXP1_227
L3 MGTHTXN1_227
K2 MGTHRXP1_227
K1 MGTHRXN1_227
J4 MGTHTXP2_227
J3 MGTHTXN2_227
GTH Bank
227
H2 MGTHRXP2_227
H1 MGTHRXN2_227
G4 MGTHTXP3_227
G3 MGTHTXN3_227
F2 MGTHRXP3_227
F1 MGTHRXN3_227
P6 MGTREFCLK0P_227
P5 MGTREFCLK0N_227
M6 MGTREFCLK1P_227
M5 MGTREFCLK1N_227
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Chapter 1: KCU105 Evaluation Board Features
Schematic Net Name
FMC_HPC_DP4_C2M_P
FMC_HPC_DP4_C2M_N
FMC_HPC_DP4_M2C_P
FMC_HPC_DP4_M2C_N
FMC_HPC_DP6_C2M_P
FMC_HPC_DP6_C2M_N
FMC_HPC_DP6_M2C_P
FMC_HPC_DP6_M2C_N
FMC_HPC_DP5_C2M_P
FMC_HPC_DP5_C2M_N
FMC_HPC_DP5_M2C_P
FMC_HPC_DP5_M2C_N
FMC_HPC_DP7_C2M_P
FMC_HPC_DP7_C2M_N
FMC_HPC_DP7_M2C_P
FMC_HPC_DP7_M2C_N
MGT_SI570_CLOCK_C_P
MGT_SI570_CLOCK_C_N
SI5328_OUT_C_P
SI5328_OUT_C_N
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Connected Connected Pin
Pin Name
A34 DP4_C2M_N
A35 DP4_C2M_P
A14 DP4_M2C_P
A15 DP4_M2C_N
B36 DP6_C2M_P
B37 DP6_C2M_N
B16 DP7_C2M_P
B17 DP7_C2M_N
A38 DP5_C2M_P
A39 DP5_C2M_N
A18 DP5_M2C_P
A19 DP5_M2C_N
B32 DP6_M2C_P
B33 DP6_M2C_N
B12 DP7_M2C_P
B13 DP7_M2C_N
11 Q1_P
12 Q1_N
28 CKOUT1_P
29 CKOUT1_N
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Connected
Device
FMC HPC
J22
Si53340
U104
Si5328B
U57
41