Xilinx KCU105 User Manual page 40

Table 1-10 lists the GTH bank 226 interface connections between FPGA U1, FMC LPC
connector J2, SFP0 connector P5, SFP1 connector P4 and MGT TX SMA connectors J29/J28,
MGT RX SMA connectors J31/J30 and MGT REFCLK SMA connectors J33/J32.
Table 1-10: KCU105 Board FPGA U1 GTH Bank 226 Connections
FPGA
Transceiver
(U1) FPGA (U1) Pin Name
Bank
Pin
AA4 MGTHTXP0_226
AA3 MGTHTXN0_226
Y2 MGTHRXP0_226
Y1 MGTHRXN0_226
W4 MGTHTXP1_226
W3 MGTHTXN1_226
V2 MGTHRXP1_226
V1 MGTHRXN1_226
U4 MGTHTXP2_226
U3 MGTHTXN2_226
GTH Bank
226
T2 MGTHRXP2_226
T1 MGTHRXN2_226
R4 MGTHTXP3_226
R3 MGTHTXN3_226
P2 MGTHRXP3_226
P1 MGTHRXN3_226
V6 MGTREFCLK0P_226
V5 MGTREFCLK0N_226
T6 MGTREFCLK1P_226
T5 MGTREFCLK1N_226
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Chapter 1: KCU105 Evaluation Board Features
Schematic Net Name
FMC_LPC_DP0_C2M_P
FMC_LPC_DP0_C2M_N
FMC_LPC_DP0_M2C_P
FMC_LPC_DP0_M2C_N
SFP1_TX_P
SFP1_TX_N
SFP1_RX_P
SFP1_RX_N
SFP0_TX_P
SFP0_TX_N
SFP0_RX_P
SFP0_RX_N
SMA_MGT_TX_P
SMA_MGT_TX_N
SMA_MGT_RX_C_P
SMA_MGT_RX_C_N
SMA_MGT_REFCLK_C_P
SMA_MGT_REFCLK_C_N
FMC_LPC_GBTCLK0_M2C_C_P
FMC_LPC_GBTCLK0_M2C_C_N
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Connected Connected Pin
Pin Name
C2 DP0_C2M_P
C3 DP0_C2M_N
C6 DP0_M2C_P
C7 DP0_M2C_N
18 TD_P
19 TD_N
13 RD_P
12 RD_N
18 TD_P
19 TD_N
13 RD_P
12 RD_N
1 SIG
1 SIG
1 SIG
1 SIG
1 SIG
1 SIG
D4 GBTCLK0_M2C_P
D5 GBTCLK0_M2C_N
Send Feedback
Connected
Device
FMC LPC
J2
SFP1 P4
SFP0 P5
SMA J29
SMA J28
SMA J31
SMA J30
SMA J33
SMA J32
FMC LPC
J2
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