User Dip Switches (Active High) - Xilinx Virtex-II Pro ML324 User Manual

Detailed Description

9. User DIP Switches (Active High)

There are 20 active-high DIP switches, as shown in
user I/O pins on the FPGA. These DIP switches can be used to generate vectors or any
other purpose that the user sees fit.
Table 10: User DIP Switches - SW1
Table 11: User DIP Switches - SW2
16
ML324
SW1
Pin
1 AA10
2 AB10
3 AC10
4 AD10
5 AE10
6 AF10
7 AG10
8 AH10
9 AB11
10 AF11
ML324
SW2
Pin
1 M10
2 N10
3 P10
4 R10
5 T10
6 U10
7 V10
8 W10
9 N11
10 T11
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Table 10 and Table 11, connected to
ML325
Pin
AM2
AP2
AR2
AT2
AU2
AV2
AW2
AD1
AE1
AF1
ML325
Pin
AH1
AJ1
AK1
AM1
AN1
AP1
AT1
AU1
AV1
AW1
Virtex-II Pro ML324 and ML325 Platform
UG063 (v1.2) May 30, 2006
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