Jumpers - Xilinx KCU105 User Manual

Jumpers

The default jumper settings are listed in
locations are shown in
Table A-2: Default Jumper Settings
Jumper Function
J5 Power on reset override select
J6 P5 SFP0 ENABLE
J7 P4 SFP1 ENABLE
J9 U40 1.25V VREF
J10 U40 1.25V VREF
J11 SYSMON_VCC5V0
J12 MAXIM REGULATOR INHIBIT
J14 U30 VADJ_1V8 ENABLE
J41 P5 SFP0_RS1
J42 P5 SFP0_RS0
J43 P5 SFP1_RS1
J44 P5 SFP1_RS0
J45 U58 M88E1111 EPHY
J47 SYSMON_VCC SELECT
J48 SYSMON_VREFP SELECT
J49 U40 1.25V VREF Vin SELECT
J74 PCIe LANE SIZE SELECT
J80 SYSMON_VP
J81 SYSMON_VN
Notes:
1. In KCU105 board Rev. D and later, J45 is deleted, U58 CONFIG4 pin F9 is tied to GND to specify the SGMII to CU with clock
functionality.
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Table
Figure A-1.
Default
2-3 GND = EXTENDED POWER-ON DELAY
1-2 ENABLE SFP0 P5 CONNECTOR
1 - 2 ENABLE SFP1 P4 CONNECTOR
OFF AGND-TO-GND FILT. L14 BYPASS
1 - 2 1 - 2 = SYSMON_GND_FILT TO GND
OFF 1 - 2 = SYSMON_VCC5V0 = FILT. SYS_5V0
OFF USED WHEN PROGRAMMING PWR. SYS.
OFF ADDITIONAL TO J12 VADJ_1V8 ENABLE
2 - 3 ENABLE LOW BANDWIDTH TX
2 - 3 ENABLE LOW BANDWIDTH RX
2 - 3 ENABLE LOW BANDWIDTH TX
2 - 3 ENABLE LOW BANDWIDTH RX
1 - 2 SGMII TO CU, WITH CLOCK
1 - 2 SYSMON_VCC = FILTERED VCCAUX_FPGA
1 - 2 SYSMON_VREFP = U40 1.25V VREF
2 - 3 U40 Vin = SYSMON_VCC
5 - 6 8-LANE CONFIGURATION
1 - 2 U1 VP pin V12 PULL DOWN 20.5K TO GND
1 - 2 U1 VN pin W11 PULL DOWN 20.5K TO GND
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Appendix A: Default Switch and Jumper Settings
A-2. The KCU105 board jumper header
Comments
(1)
Figure Schematic
A-1 0381556
Callout Page
1 3
2 27
3 28
4 43
5 43
6 43
7 51
8 56
9 27
10 27
11 28
12 28
13 38
14 43
15 43
16 43
17 26
18 3
19 3
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