Xilinx KCU105 User Manual page 46

Table 1-13 lists the SFP+ module connections to FPGA U1.
Table 1-13: KCU105 Board FPGA U1 to SFP0 and SFP1 Module Connections
FPGA (U1)
Schematic Net Name
Pin
T2
T1
U4
U3
AL8
V2
V1
W4
W3
AM9
Notes:
1. SFP0_TX_DISABLE, SFP1_TX_DISABLE I/O standard LVCMOS18; MGT connections I/O standard not applicable.
Table 1-14: SFP0 and SFP1 Module Control and Status Connections
SFP Control/Status
Signal
SFP_TX_FAULT
SFP_TX_DISABLE
SFP_MOD_DETECT
SFP_RS0
SFP_RS1
SFP_LOS
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
FPGA (U1)
Direction
SFP0_RX_P Input
SFP0_RX_N Input
SFP0_TX_P Output
SFP0_TX_N Output
SFP0_TX_DISABLE Output
SFP1_RX_P Input
SFP1_RX_N Input
SFP1_TX_P Output
SFP1_TX_N Output
SFP1_TX_DISABLE Output
High = Fault
Test Point J16
Low = Normal operation
Off = SFP Disabled
Jumper J6
On = SFP Enabled
High = Module not present
Test Point J17
Low = Module present
Jumper pins 1-2 = Full RX bandwidth
Jumper J42
Jumper pins 2-3 = Reduced RX bandwidth
Jumper pins 1-2 = Full RX bandwidth
Jumper J41
Jumper pins 2-3 = Reduced RX bandwidth
High = Loss of receiver signal
Test Point J18
Low = Normal operation
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Chapter 1: KCU105 Evaluation Board Features
Pin
Number
13
12
18
19
3
13
12
18
19
3
Board Connection
SFP/SFP+
Pin Name
Module
RD_P
RD_N
TD_P SFP0 P5
TD_N
TX_DISABLE
RD_P
RD_N
TD_P SFP1 P4
TD_N
TX_DISABLE
SFP
Module
SFP0 P5
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