Xilinx KCU105 User Manual page 22

The connections between the SPI flash memories and the XCKU040 device are listed in
Table 1-5.
Table 1-5: Quad-SPI Flash Memory Connections to FPGA U1
FPGA (U1) Schematic Net
Pin Name
AC7 QSPI0_IO0
AB7 QSPI0_IO1
AA7 QSPI0_IO2
Y7 QSPI0_IO3
AA9 FPGA_CCLK
U7 QSPI0_CSB
M20 QSPI1_IO0
L20 QSPI1_IO1
R21 QSPI1_IO2
R22 QSPI1_IO3
G26 QSPI1_CSB
Notes:
1. CCLK is a dedicated pin and does not require an IOSTANDARD or LOC attribute.
Figure 1-6 shows the connections of the linear Quad-SPI flash memory on the KCU105
evaluation board. For more details, see the Micron N25Q256A11ESF40F data sheet at the
Micron website
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
I/O Standard
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
(1)
NA
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
[Ref 22].
www.xilinx.com
Chapter 1: KCU105 Evaluation Board Features
Pin # Pin Name
15 SI_IO0
8 SI_IO1
9 SI_IO2
1 SI_IO3
16 SCK
7 CS_B
15 SI_IO0
8 SI_IO1
9 SI_IO2
1 SI_IO3
7 CS_B
Ref. Des.
U35
U35
U35
U35
U35, U36
U35
U36
U36
U36
U36
U36
22
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