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Xilinx KCU116 User Manual

Xilinx KCU116 User Manual

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KCU116 Evaluation Board
User Guide
UG1239 (v1.2) September 28, 2018

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Summary of Contents for Xilinx KCU116

  • Page 1 KCU116 Evaluation Board User Guide UG1239 (v1.2) September 28, 2018...

  • Page 2: Revision History

    DDR4 Component Memory Regulatory and Compliance Information. Added Electrostatic Discharge Caution. 05/03/2018 Updated Figure 3-19 Table 3-18. 06/08/2017 1.0.2 Typographical update. 05/15/2017 1.0.1 Typographical update. 05/12/2017 Initial Xilinx release. KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 3: Table Of Contents

    Installing the KCU116 Board in a PC Chassis ....... . .
  • Page 4 KCU116 Board Power System ........

  • Page 5: Chapter 1: Introduction

    The KCU116 evaluation board for the Xilinx Kintex UltraScale+ FPGA provides a hardware environment for developing and evaluating designs targeting the UltraScale+ XCKU5P-2FFVB676E device. The KCU116 evaluation board provides features common to many evaluation systems, including: • DDR4 component memory ™...

  • Page 6: Block Diagram

    X-Ref Target - Figure 1-1 X18245-120916 Figure 1‐1: KCU116 Evaluation Board Block Diagram Board Features The KCU116 evaluation board features are listed in this section. Detailed information for each feature is provided in Component Descriptions in Chapter • Kintex UltraScale+ XCKU5P-2FFVB676E FPGA ®...
  • Page 7 • Power management with PMBus voltage monitoring through Maxim power controllers and GUI • Single 10-bit 0.2 MSPS ADC system monitor (SYSMON) analog-to-digital front end • Configuration options: KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 8: Board Specifications

    Thickness (±5%): 0.061 inch (0.1549 cm) Length: 9.5 inch (24.13 cm) A 3D model of this board is not available. Note: The KCU116 board height exceeds the standard 4.376 inch (11.15 cm) height of a PCI IMPORTANT: Express card. Environmental Temperature Operating: 0°C to +45°C...

  • Page 9: Chapter 2: Board Setup And Configuration

    • Put the adapter down only on an antistatic surface such as the bag supplied in your kit. • If you are returning the adapter to Xilinx Product Support, place it back in its antistatic bag immediately. Board Component Location Figure 2-1 shows the KCU116 board component locations.
  • Page 10 X-Ref Target - Figure 2-1 Round callout references a component Square callout references a component on the front side of the board on the back side of the board X18418-041717 Figure 2‐1: KCU116 Evaluation Board Components Table 2‐1: KCU116 Board Component Descriptions Schematic Callout Feature Notes...
  • Page 11 Chapter 2: Board Setup and Configuration Table 2‐1: KCU116 Board Component Descriptions (Cont’d) Schematic Callout Feature Notes Page Number User SMA Clock, user differential SMA clock P/N Rosenberger 32K10K-400L5 (J168/J169) User SMA GPIO, user SMA GPIO connectors P/N Rosenberger 32K10K-400L5 (J178/J179) GTY Transceivers...

  • Page 12: Default Switch And Jumper Settings

    Chapter 2: Board Setup and Configuration Table 2‐1: KCU116 Board Component Descriptions (Cont’d) Schematic Callout Feature Notes Page Number Monitoring Voltage and Current, 2x8 shrouded ASSMAN AWHW16G-0202 PMBus connector (J84) KCU116 Board Power System, power management Maxim MAX15301, MAX15303 and 44-58 system (top and bottom) MAX20751 Digital P.O.L.

  • Page 13: Jumpers

    Chapter 2: Board Setup and Configuration Jumpers Figure 2-2 shows the KCU116 board jumper header locations. Each numbered component shown in the figure is keyed to Table 2-3, which identifies the default jumper settings and references the respective schematic page numbers.

  • Page 14: Installing The Kcu116 Board In A Pc Chassis

    Figure 2-3. a. Plug the 6-pin 2 x 3 Molex connector on the adapter cable into J52 on the KCU116 board. b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the 4-pin adapter cable connector.

  • Page 15: Fpga Configuration

    The ATX 6-pin connector has a different pin out than J52. Connecting an ATX 6-pin connector into J52 damages the KCU116 evaluation board and voids the board warranty. 8. Slide the KCU116 board power switch SW1 to the ON position. The PC can now be powered on.

  • Page 16: Chapter 3: Board Component Descriptions

    For more information on Kintex UltraScale+ FPGAs, see Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922) [Ref Encryption Key Battery Backup Circuit The XCKU5P device U1 implements bitstream encryption key technology. The KCU116 board provides the encryption key backup battery circuit shown in Figure 3-1. The Seiko TS518FE rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the...
  • Page 17 Chapter 3: Board Component Descriptions X-Ref Target - Figure 3-1 X18285-120916 Figure 3‐1: Encryption Key Backup Circuit KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 18 Chapter 3: Board Component Descriptions I/O Voltage Rails There are seven I/O banks available on the XCKU5P device and the KCU116 board. The voltages applied to the FPGA I/O banks (shown in Figure 3-2) used by the KCU116 board are listed in Table 3-1.

  • Page 19: Ddr4 Component Memory

    ° DDR4-2666 ° The KCU116 XCKU5P FPGA DDR memory interface performance is documented in the Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922) [Ref This memory system is connected to the XCKU5P device HP banks 66 and 67.
  • Page 20 DDR4_DQ29 POD12_DCI DQU5 U153 DDR4_DQ30 POD12_DCI DQU6 U153 DDR4_DQ31 POD12_DCI DQU7 U153 DDR4_DQS2_T DIFF_POD12_DCI DQSL_T U153 DDR4_DQS2_C DIFF_POD12_DCI DQSL_C U153 DDR4_DQS3_T DIFF_POD12_DCI DQSU_T U153 DDR4_DQS3_C DIFF_POD12_DCI DQSU_C U153 KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 21 DDR4_ODT SSTL12 U150, U153 DDR4_CS_B SSTL12 CS_B U150, U153 DDR4_CKE SSTL12 U150, U153 DDR4_RESET_B LVCMOS12 RESET_B U150, U153 DDR4_CK_T DIFF_SSTL12_DCI CK_T U150, U153 DDR4_CK_C DIFF_SSTL12_DCI CK_C U150, U153 KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 22 Chapter 3: Board Component Descriptions The KCU116 dual DDR4 memory component interface adheres to the constraints guidelines documented in the “DDR3/DDR4 Design Guidelines” section of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) [Ref 5]. The KCU116 board DDR4 memory component interface is a 40 impedance implementation.

  • Page 23: Dual Quad Spi Flash Memory

    QSPI1_DQ1 LVCMOS18 QSPI1_DQ2 LVCMOS18 DQ2/VPP/WP_B QSPI1_DQ3 LVCMOS18 DQ3/HOLD_B QSPI_CLK QSPI1_CS_B LVCMOS18 Notes: 1. For details on bank 0 pins, see the UltraScale Architecture Configuration User Guide (UG570) [Ref KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 24 Chapter 3: Board Component Descriptions Figure 3-3 shows the linear Quad SPI flash memory circuitry on the KCU116 evaluation board. For more details, see the Micron MT25QU01GBBB8ESF-0SIT data sheet at the Micron website [Ref 23]. X-Ref Target - Figure 3-3 X18287-120916 Figure 3‐3: Dual Quad SPI 2 Gb Flash Memory...

  • Page 25: Micro-Sd Card Interface

    Chapter 3: Board Component Descriptions Micro‐SD Card Interface [Figure 2-1, callout 4] The KCU116 board includes a secure digital input/output (SDIO) interface allowing the U161 ® XC7Z010 Zynq -7000 SoC system controller access to general purpose nonvolatile micro-SD memory cards and peripherals. The micro-SD card slot is designed to support 50 MHz high speed micro-SD cards.

  • Page 26: Usb Jtag Interface

    FPGA mode pin settings. JTAG initiated configuration takes priority over the configuration method selected through the FPGA mode pin M2 (which is wired to DIP SW21 pin 6, switch position 6). The JTAG chain of the KCU116 board is shown Figure 3-5.

  • Page 27: Fmc Connector Jtag Bypass

    Figure 3‐5: JTAG Chain Block Diagram FMC Connector JTAG Bypass When an FMC is attached to the KCU116 board, it is automatically added to the JTAG chain through an electronically controlled single-pole single-throw (SPST) switch U27. The SPST switch is in a normally closed state and transitions to an open state when the FMC is attached to J5.

  • Page 28: Clock Generation

    Chapter 3: Board Component Descriptions Clock Generation [Figure 2-1, callout 6] The KCU116 evaluation board provides eight clock sources to the XCKU5P device as listed in Table 3-5. Table 3‐5: KCU116 Board Clock Sources Clock Name Clock Ref. Des. Description Silicon Labs Si5335A 1.8V LVDS any frequency quad...

  • Page 29: System Clock

    Chapter 3: Board Component Descriptions Table 3-6 lists the FPGA connections for each clock. Table 3‐6: KCU116 Clock Sources to XCKU5P FPGA U1 Connections Clock Source XCKU5P FPGA Schematic Net Name I/O Standard Ref.Des. and Pin (U1) Pin U170.22 SYSCLK_300_P LVDS U170.21...
  • Page 30 Figure 3-6. X-Ref Target - Figure 3-6 X18289-120916 Figure 3‐6: KCU116 System Clock Three additional clocks are sourced from the U170 quad clock generator: • 125 MHz LVDS signal pair CLK_125MHZ_P and CLK_125MHZ_N, connected to XCKU5P FPGA U1 bank 87 pins G12 and F12, respectively.

  • Page 31: Programmable Mgt User Clock

    Programmable MGT User Clock [Figure 2-1, callout 7] The KCU116 evaluation board has a SI570 programmable low-jitter 3.3V LVDS differential oscillator (U56) connected (series capacitor AC coupled) to the FPGA U1 MGTY226 MGTREFCLK1 P/N inputs (pin M7 (P) and M6 (N)).

  • Page 32: User Sma Clock

    Chapter 3: Board Component Descriptions User SMA Clock [Figure 2-1, callout 9] The KCU116 board provides a pair of SMAs for differential user clock input into FPGA U1 bank 66 (see Figure 3-8). The P-side SMA J168 signal USER_SMA_CLOCK_P is connected to U1 GC pin J23, with the N-side SMA J169 signal USER_SMA_CLOCK_N connected to U1 GC pin J24.

  • Page 33: Jitter Attenuated Clock

    [Figure 2-1, callout 8] The KCU116 board includes a Silicon Labs SI5328C jitter attenuator U20. FPGA U1 user logic can implement a clock recovery circuit and then output this clock from a differential pair on I/O bank 84 (SFP_REC_CLOCK_P, FPGA U1 pin AB15 and SFP_REC_CLOCK_N, U1 pin AAB16) for jitter attenuation.

  • Page 34: Video Clock

    [Figure 2-1, near callout 6, bottom of board] The KCU116 evaluation board has a SI511B low-jitter 3.3V LVDS fixed frequency 74.25 MHz differential LVDS oscillator (U179) connected to the FPGA U1 bank 86 inputs pin D11 (P) and D10 (N).

  • Page 35: Gty Transceivers

    The GTY transceivers in the XCKU5P are grouped into four channels or quads. The reference clock for a quad can be sourced from the quad above or the quad below the GTY quad of interest. There are four GTY quads on the KCU116 board with connectivity as listed here (see Figure...
  • Page 36 MGT_227_0 FMC_HPC0_DP_0 MGT_225_1 PCIE_2 MGT_227_1 FMC_HPC0_DP_1 MGT_225_2 PCIE_1 MGT_227_2 FMC_HPC0_DP_2 MGT_225_3 FMC_HPC0_DP_3 PCIE_0 MGT_227_3 MGT_225_REFCLK_0 PCIE_CLK_Q0 MGT_227_REFCLK_0 FMC_HPC0_GBTCLK0 Not connected MGT_225_REFCLK_1 MGT_227_REFCLK_1 FMC_HPC0_GBTCLK1 X18998-042017 Figure 3‐11: GTY Bank Assignments KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 37 Chapter 3: Board Component Descriptions Table 3-7 lists the GTY Banks 224 and 225 interface connections between FPGA U1 and 8-lane PCIe connector P1. Table 3‐7: KCU116 FPGA U1 GTY Banks 224 and 225 Connections to PCIe Connector P1 Transceiver FPGA Schematic Net...
  • Page 38 Chapter 3: Board Component Descriptions Table 3‐7: KCU116 FPGA U1 GTY Banks 224 and 225 Connections to PCIe Connector P1 (Cont’d) Transceiver FPGA Schematic Net Connected Connected Connected FPGA (U1) Pin Name Bank (U1) Pin Name Pin Name Device MGTYTXP0_225 PCIE_TX3_P PERp3...
  • Page 39 Chapter 3: Board Component Descriptions Table 3-8 lists the GTY Bank 226 interface connections between FPGA U1 and the four zSFP connectors J1, J3, J4 and J6. Table 3‐8: KCU116 FPGA U1 GTY Bank 226 Connections FPGA Connected Connected Connected (U1) FPGA (U1) Pin Name...
  • Page 40 Chapter 3: Board Component Descriptions Table 3-9 lists the GTY Bank 227 interface connections between FPGA U1 and FMC HPC0 connector J5 Table 3‐9: KCU116 FPGA U1 GTY Bank 227 Connections FPGA FPGA (U1) Pin Connected Connected Pin Connected (U1) Schematic Net Name...

  • Page 41: Pci Express Endpoint Connectivity

    PCIe P1 to FPGA U1 connectivity details. The XCKU5P-2FFVB676E device (-2 speed grade) included with the KCU116 board supports up to Gen3 x8. The PCIe clock is input from the P1 edge connector. It is AC coupled to FPGA U1 through the MGTREFCLK0 pins of Quad 225.

  • Page 42: Zsfp/Zsfp+ Module Connectors

    Module Connectors [Figure 2-1, callouts 14, 15] The KCU116 board hosts four zSFP/zSFP+ J1, J3, J4, and J6 that accept zSFP or zSFP+ modules. The connectors are housed within a single quad zSFP cage assembly. Figure 3-14 shows the zSFP/zSFP+ module connector circuitry typical of the four implementations.
  • Page 43 Chapter 3: Board Component Descriptions Table 3‐10: KCU116 FPGA U1 to zSFP0‐zSFP3 Module Connections (Cont’d) Schematic Net FPGA (U1) Pin Pin Number Pin Name SFP/SFP+ Module Name SFP1_RX_P RD_P SFP1_RX_N RD_N SFP1_TX_P TD_P zSFP1 J3 SFP1_TX_N TD_N AA14 SFP1_TX_DISABLE_B TX_DISABLE SFP2_RX_P RD_P...
  • Page 44 PU R227 = Full RX bandwidth (1)(2) SFP_RS1 PU R304/ PD R588 PD R142 = Reduced RX bandwidth High = Loss of receiver signal SFP_LOS Test Point J59 Low = Normal operation KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 45 2. Also available via I2C control. For this and additional information about the enhanced SFP+ module, see the SFF-8431 specification at the SFF-8431 specification website [Ref 29]. KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 46: 10/100/1000 Mb/S Tri-Speed Ethernet Phy

    [Figure 2-1, callout 16] The KCU116 board uses the TI DP83867ISRGZ Ethernet SGMII PHY at U12 for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports SGMII mode only. The PHY connection to a user-provided Ethernet cable is through a Wurth 7499111221A RJ-45 connector (P3) with built-in magnetics.
  • Page 47 Schematic Net Name Name PHY1_MDIO MDIO PHY1_MDC PHY1_PDWN_B_I_INT_B_O INT_PWDN PHY1_SGMII_IN_P TX_D1_SGMII_SIP PHY1_SGMII_IN_N TX_D0_SGMII_SIN PHY1_SGMII_OUT_P RX_D2_SGMII_SOP PHY1_SGMII_OUT_N RX_D3_SGMII_SON PHY1_SGMII_CLK_P RX_D0_SGMII_COP PHY1_SGMII_CLK_N RX_D1_SGMII_CON AA23 PHY1_RESET_B RESET_B PHY1_CLKOUT CLK_OUT PHY1_GPIO_0 GPIO_2 KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 48: Ethernet Phy Status Leds

    P3 RJ-45 connector. These LEDs are visible on the left edge of the KCU116 board when it is installed into a PCIe slot in a PC chassis. The two PHY status LEDs are visible within the frame of the RJ-45 Ethernet jack as shown in Figure 3-16.

  • Page 49: Dual Usb-To-Uart Bridge

    (U166) that allows a connection to a host computer with a USB port. The USB cable is supplied in the KCU116 evaluation kit (standard type-A end to host computer, type micro-B end to KCU116 evaluation board connector J164). The CP2105GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the KCU116 evaluation board.
  • Page 50 Figure 3-17. X-Ref Target - Figure 3-17 X18518-042017 Figure 3‐17: KCU116 Dual UART CP2105GM Table 3-14 lists the CP2105GM connections to FPGA U1. The USB UART schematic nets are named from the perspective of the CP2105GM device (U166). Table 3‐14: FPGA U1 to CP2105GM U166 Connections...

  • Page 51: Hdmi Video Output

    For more technical information on the CP2105GM and the VCP drivers, see the Silicon Labs website [Ref 27]. Xilinx UART IP is expected to be implemented in the FPGA logic using IP. See the AXI UART Lite LogiCORE IP Product Guide (PG142) [Ref 11] for more information.
  • Page 52 Chapter 3: Board Component Descriptions The HDMI U5 circuit is shown in Figure 3-18. X-Ref Target - Figure 3-18 X18529-042017 Figure 3‐18: HDMI Codec Circuit KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 53 SPDIF_OUT HDMI_INT LVCMOS18 Notes: All HDMI nets in this table, except HDMI_INT, are series resistor coupled. All HDMI nets in this table except HDMI_INT are series resistor coupled. KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 54: I2C Bus

    19]. I2C Bus [Figure 2-1, callouts 20, 21] The KCU116 evaluation board implements a 2-to-1 I C bus arrangement. A single I C bus from each of the FPGA U1 XCKU5P (IIC_MAIN_SCL/SDA_LS) and system controller Zynq-7000 SoC U111 (SYSCTLR_I2C_SCL/SDA) are wired to the same I...
  • Page 55 Chapter 3: Board Component Descriptions The KCU116 evaluation board I C bus topology is shown in Figure 3-19. X-Ref Target - Figure 3-19 UTIL_3V3 to SYS_1V8 U168 Maxim power regulators Level MAXIM_CABLE_B U163 shifters Maxim IIC_MAIN BANK BANK Level cable shifter...
  • Page 56 SFP0_IIC_SDA/SCL J1 SFP0 0b1010000 TCA6416 I C Port Expander 0x21 U147 TCA6416 0b0100001 Information about the PCA9548A and TCA6416A is available on the TI Semiconductor website [Ref 31]. KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 57: Status And User Leds

    Chapter 3: Board Component Descriptions Status and User LEDs [Figure 2-1, callout 22] Table 3-19 defines KCU116 board status and user LEDs. Table 3‐19: KCU116 Board Status and User LEDs Reference Designator Description INIT 12V On VCCAUX_PGOOD VCC3V3_PGOOD VCCINT_PGOOD VADJ_FMC_PGOOD VCC1V2_PGOOD VCCBRAM_PGOOD...

  • Page 58: User I/O

    EPHY P3 (Left) LED ENET PHY Activity User I/O [Figure 2-1, callouts 22, 23, 24, 25] The KCU116 board provides these user and general purpose I/O capabilities: • Eight user LEDs (callout 22) GPIO_LED[7-0]: DS44, DS43, DS42, DS41, DS40, DS39, DS37, DS38 °...

  • Page 59: User Gpio Leds

    Chapter 3: Board Component Descriptions User GPIO LEDs [Figure 2-1, callout 22] Figure 3-20 shows the GPIO LED circuit. X-Ref Target - Figure 3-20 X18533-042017 Figure 3‐20: User LEDs KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 60: User Pushbuttons

    Chapter 3: Board Component Descriptions User Pushbuttons [Figure 2-1, callout 24] Figure 3-21 shows the user pushbuttons circuit. X-Ref Target - Figure 3-21 X18534-042017 Figure 3‐21: User Pushbuttons KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 61: User Sma Gpio

    User SMA GPIO [Figure 2-1, callout 10] The KCU116 board provides a pair of SMAs for differential user I/O into FPGA U1 bank 66 (see Figure 3-22). The P-side SMA J178 signal USER_SMA_P is connected to U1 pin K25, and the N-side SMA J179 signal USER_SMA_N is connected to U1 pin K26.

  • Page 62: Cpu Reset Pushbutton

    Chapter 3: Board Component Descriptions CPU Reset Pushbutton [Figure 2-1, callout 24] Figure 3-23 shows the CPU reset pushbutton circuit. X-Ref Target - Figure 3-23 X18535-042017 Figure 3‐23: CPU Reset Pushbutton KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 63: Gpio Dip Switch

    GPIO DIP switch circuit. X-Ref Target - Figure 3-24 X18537-042017 Figure 3‐24: GPIO DIP Switch Table 3-20 lists the GPIO connections to FPGA U1. Table 3‐20: KCU116 GPIO Connections to FPGA U1 Schematic Net FPGA Pin (U1) I/O Standard GPIO Name...

  • Page 64: User Pmod Gpio Headers

    [Figure 2-1, callout 28] The KCU116 evaluation board supports two Pmod GPIO headers J55 and J87. The Pmod nets are connected to FPGA U1 Bank 87. Pmod connector J55 is a right-angle receptacle and connector J87 is a vertical male pin header.

  • Page 65: Switches

    [Ref 26]. Switches [Figure 2-1, callouts 27, 31] The KCU116 evaluation board includes a power on/off slide switch and a configuration pushbutton switch: • Power on/off slide switch SW1 (callout 31) • FPGA PROG_B SW4, active-Low (callout 27) KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018...
  • Page 66 [Figure 2-1, callout 30] The KCU116 board power switch is SW1. Sliding the switch actuator from the off to on position applies 12VDC power from the 6-pin mini-fit power input connector J52. The green LED DS2 illuminates when the KCU116 board power is on. See KCU116 Board Power System for details on the onboard power system.

  • Page 67: Program_B Pushbutton Switch

    AB9. See UltraScale Architecture Configuration User Guide (UG570) [Ref 3] for further configuration details. Figure 3-28 shows SW4. X-Ref Target - Figure 3-28 X18539-121616 Figure 3‐28: Program_B Pushbutton Switch SW5 KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 68: Fpga Mezzanine Card Interface

    • 1 differential clock • 159 ground and 11 power connections The KCU116 board FMC VADJ voltage VADJ_FMC for the J5 FMC connector is determined by the MAX15301 U63 voltage regulator described in KCU116 Board Power System. KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018...
  • Page 69 Schematic Net Name Schematic Net Name Standard (U1) Pin Standard (U1) Pin FMC_HPC0_DP1_M2C_P FMC_HPC0_DP1_M2C_N FMC_HPC0_DP2_M2C_P FMC_HPC0_DP2_M2C_N FMC_HPC0_DP3_M2C_P FMC_HPC0_DP3_M2C_N FMC_HPC0_GBTCLK1_M2C_P LVDS FMC_HPC0_DP1_C2M_P FMC_HPC0_GBTCLK1_M2C_N LVDS FMC_HPC0_DP1_C2M_N FMC_HPC0_DP2_C2M_P FMC_HPC0_DP2_C2M_N FMC_HPC0_DP3_C2M_P FMC_HPC0_DP3_C2M_N KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 70 LVDS AD21 FMC_HPC0_LA17_CC_N LVDS AE21 FMC_HPC0_IIC_SCL FMC_HPC0_IIC_SDA GA0 = 0 = GND VCC12_SW FMC_HPC0_TCK_BUF VCC12_SW FPGA_TDO_FMC_TDI_BUF UTIL_3V3 FMC_HPC0_TDO UTIL_3V3 FMC_HPC0_TMS_BUF GA1 = 0 = GND UTIL_3V3 UTIL_3V3 UTIL_3V3 KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 71 Table 3‐24: J5 HPC FMC Section E/F Connections to FPGA U1 U1 FPGA U1 FPGA Schematic Net Name J5 Pin Schematic Net Name Standard Standard FMC_HPC0_PG_M2C LVCMOS33 VADJ _FMC_BUS VADJ _FMC_BUS KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 72 FMC_HPC0_LA20_N LVDS AF25 FMC_HPC0_LA15_N LVDS AC24 FMC_HPC0_LA22_P LVDS AE25 FMC_HPC0_LA19_P LVDS AC26 FMC_HPC0_LA22_N LVDS AE26 FMC_HPC0_LA19_N LVDS AD26 FMC_HPC0_LA21_P LVDS AB25 FMC_HPC0_LA21_N LVDS AB26 VADJ _FMC_BUS VADJ _FMC_BUS KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 73 Chapter 3: Board Component Descriptions Table 3‐26: J5 HPC FMC Section J/K Connections to FPGA U1 Schematic Net U1 FPGA Schematic Net U1 FPGA I/O Standard J5 Pin I/O Standard Name Name KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 74: Kcu116 Board Power System

    Chapter 3: Board Component Descriptions KCU116 Board Power System [Figure 2-1, callout 33] The KCU116 hosts a Maxim PMBus based power system. Each individual Maxim MAX15301, MAX15303, and MAX20751 voltage regulator has a PMBus interface. Figure 3-29 shows the KCU116 power system block diagram.
  • Page 75 Chapter 3: Board Component Descriptions The KCU116 evaluation board uses power regulators and PMBus compliant point of load (POL) controllers from Maxim Integrated Circuits to supply the core and auxiliary voltages listed in Table 3-27. Table 3‐27: Onboard Power System Devices INA226 Power...

  • Page 76: Sysmon Header J93

    ADC mode. See the UltraScale Architecture System Monitor User Guide (UG580) [Ref 20] for details on the capabilities of the analog front end. Figure 3-30 shows the KCU116 board SYSMON support features. KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...
  • Page 77 Header X18424-120916 Figure 3‐30: KCU116 SYSMON and SYSMON Header J93 Voltage Source Options The KCU116 board supports both the internal FPGA sensor measurements and the external measurement capabilities of the SYSMON. Internal measurements of the die temperature, , and V are available. Header J90 can be used to select either an...
  • Page 78 Chapter 3: Board Component Descriptions Figure 3-31 shows the header connections. X-Ref Target - Figure 3-31 X18540-042017 Figure 3‐31: SYSMON Header J93 KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 79: System Controller

    A host PC resident graphical user interface for the system controller (SCUI) is provided on the KCU116 website. The SCUI can be used to query and control select programmable features such as clocks, FMC functionality, and power systems.
  • Page 80 EEPROM Voltage. The SCUI buttons are grayed out during command execution and return to their original appearance when ready to accept a new command. See Figure 3-32. See the KCU116 System Controller Tutorial (XTP465) [Ref 16] and the KCU116 Software Install and Board Setup Tutorial (XTP464)

  • Page 81: Appendix A: Vita 57.1 Fmc Connector Pinout

    Figure A-1 shows the pinout of the FPGA mezzanine card (FMC) high pin count (HPC) J5 defined by the VITA 57.1 FMC specification. For a description of how the KCU116 evaluation board implements the FMC specification, see FPGA Mezzanine Card Interface, page...

  • Page 82: Appendix B: Xilinx Constraints File

    The Xilinx design constraints (XDC) file template for the KCU116 board is for designs targeting the KCU116 evaluation board. Net names in the constraints correlate with net names on the latest KCU116 evaluation board schematic. Users must identify the appropriate pins and replace the net names with net names in the user RTL. See the Vivado...

  • Page 83: Appendix C: Regulatory And Compliance Information

    Regulatory and Compliance Information Overview This product is designed and tested to conform to the European Union directives and standards described in this section. KCU116 Evaluation Kit — Master Answer Record (AR 68360) For Technical Support, open a Support Service Request.

  • Page 84: Safety

    This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment. This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive. KCU116 Board User Guide Send Feedback UG1239 (v1.2) September 28, 2018 www.xilinx.com...

  • Page 85: Appendix D: Additional Resources And Legal Notices

    Documentation Navigator and Design Hubs Xilinx® Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav): • From the Vivado® IDE, select Help > Documentation and Tutorials.

  • Page 86: References

    Appendix D: Additional Resources and Legal Notices References The most up to date information related to the KCU116 board and its documentation is available on the following websites. KCU116 Evaluation Kit KCU116 Evaluation Kit — Master Answer Record (AR 68360) These Xilinx documents provide supplemental material useful with this guide: 1.
  • Page 87 InTune™ Digital PowerTool Software Version 1.08.02 is available. Users will have to create a Maxim account and login before they can see the link to download the GUI. 35. The Xilinx ATX cable part number 2600304 is manufactured by Sourcegate Technologies and is equivalent to the Sourcegate Technologies part number AZCBL-WH-11009.

  • Page 88: Please Read: Important Legal Notices

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

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