Xilinx KCU105 User Manual page 54

Table 1-18 lists the HDMI Codec U52 to the XCKU040 device U1 connections. All HDMI nets
in this table are series resistor coupled.
Table 1-18: HDMI Codec U52 to XCKU040 Device U1 Connections
FPGA (U1) Schematic Net
Pin Name
AK11 HDMI_D0
AP11 HDMI_D1
AP13 HDMI_D2
AN13 HDMI_D3
AN11 HDMI_D4
AM11 HDMI_D5
AN12 HDMI_D6
AM12 HDMI_D7
AL12 HDMI_D8
AK12 HDMI_D9
AL13 HDMI_D10
AK13 HDMI_D11
AD11 HDMI_D12
AH12 HDMI_D13
AG12 HDMI_D14
AJ11 HDMI_D15
AE11 HDMI_DE
AE12 HDMI_SPDIF
AF13 HDMI_CLK
AH13 HDMI_VSYNC
AE13 HDMI_HSYNC
AJ13 HDMI_INT
AF12 HDMI_SPDIF_OUT
Notes:
1. The HDMI_INT net is direct coupled (no series resistor).
For more information about the Analog Devices ADV7511KSTZ-P, see the Analog Devices
website [Ref 32]. For additional information about HDMI IP options, see the DisplayPort
LogiCORE Product Guide (PG064)
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
FPGA (U1)
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
(1)
Input
Input
[Ref 10].
www.xilinx.com
Chapter 1: KCU105 Evaluation Board Features
I/O Standard
Pin Number
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
ADV7511 U52
Name
88 D8
87 D9
86 D10
85 D11
84 D12
83 D13
82 D14
81 D15
80 D16
78 D17
74 D18
73 D19
72 D20
71 D21
70 D22
69 D23
97 DE
10 SPDIF
79 CLK
2 VSYNC
98 HSYNC
45 INT
46 SPDIF_OUT
54
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