Xilinx KCU105 User Manual page 38

Quad 227:
• MGTREFCLK0 - MGT_SI570_CLOCK_C_P/N clock
• MGTREFCLK1 - SI5328_OUT_C_P/N jitter attenuator clock
• Contains four GTH transceivers allocated to FMC_HPC_DP[7:4]_C2M_P/N
Quad 228:
• MGTREFCLK0 - FMC_HPC_GBTCLK0_M2C_C_P/N clock
• MGTREFCLK1 - FMC_HPC_GBTCLK1_M2C_C_P/N clock
• Contains four GTH transceivers allocated to FMC_HPC_DP[3:0]_C2M/M2C_P/N
Table 1-9 lists the GTH banks 224 and 225 interface connections between FPGA U1 and
8-lane PCIe connector P1.
Table 1-9: KCU105 Board FPGA U1 GTH Banks 224 and 225 Connections to PCIe Connector P1
Transceiver FPGA
Bank (U1) Pin
AN4 MGTHTXP0_224
AN3 MGTHTXN0_224
AP2 MGTHRXP0_224
AP1 MGTHRXN0_224
AM6 MGTHTXP1_224
AM5 MGTHTXN1_224
AM2 MGTHRXP1_224
AM1 MGTHRXN1_224
AL4 MGTHTXP2_224
AL3 MGTHTXN2_224
GTH Bank
224
AK2 MGTHRXP2_224
AK1 MGTHRXN2_224
AK6 MGTHTXP3_224
AK5 MGTHTXN3_224
AJ4 MGTHRXP3_224
AJ3 MGTHRXN3_224
AF6 MGTREFCLK0P_224
AF5 MGTREFCLK0N_224
AD6 MGTREFCLK1P_224
AD5 MGTREFCLK1N_224
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
FPGA (U1) Pin Name
www.xilinx.com
Chapter 1: KCU105 Evaluation Board Features
Schematic Net Connected
Name Pin
PCIE_TX7_P A47
PCIE_TX7_N A48
PCIE_RX7_P B45
PCIE_RX7_N B46
PCIE_TX6_P A43
PCIE_TX6_N A44
PCIE_RX6_P B41
PCIE_RX6_N B42
PCIE_TX5_P A39
PCIE_TX5_N A40
PCIE_RX5_P B37
PCIE_RX5_N B38
PCIE_TX4_P A35
PCIE_TX4_N A36
PCIE_RX4_P B33
PCIE_RX4_N B34
NC
NC
NC
NC
Connected Connected
Pin Name
PERp7
PERn7
PETp7
PETn7
PERp6
PERn6
PETp6
PETn6
PERp5
PCIe Edge
PERn5
Connector
PETp5
PETn5
PERp4
PERn4
PETp4
PETn4
NA NA
NA NA
NA NA
NA NA
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Device
P1
38