Xilinx KCU105 User Manual page 48

On power-up, or on reset, the PHY is configured to operate in SGMII mode with PHY
address 0b00111 using the settings shown in
written via software commands passed over the MDIO interface.
Table 1-15: Board Connections for PHY Configuration Pins
Pin Bit[2]
CFG0 PHYADR[2]
CFG1 ENA_PAUSE
CFG2 ANEG[3]
CFG3 ANEG[0]
CFG4 HWCFG_MD[2]
CFG5 DIS_FC
CFG6 SEL_BDT
Table 1-16: FPGA U1 to Ethernet PHY U58 Connections
FPGA (U1)
Pin
H26
L25
K25
J23
Notes:
Ethernet PHY_ U58 signals are level-shifted to 1.8V for interface to FPGA U1 bank 65.
X-Ref Target - Figure 1-19
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Bit[1]
PHYADR[1]
PHYADR[4]
ANEG[2]
ENA_XC
HWCFG_MD[1]
DIS_SLEEP
INT_POL
Net Name I/O Standard
PHY_MDIO LVCMOS18
PHY_MDC LVCMOS18
PHY_INT LVCMOS18
PHY_RESET LVCMOS18
Figure 1-19: Ethernet PHY J45 Configuration Jumper J45
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Chapter 1: KCU105 Evaluation Board Features
Table 1-15. These settings can be over
Default
Bit[0] Values for
Bit[2:0]
PHYADR[0] 111
PHYADR[3] 000
ANEG[1] 111
DIS_125 111
HWCFG_MD[0] 100
HWCFG_MD[3] 110
75/50 Ω 010
M88E1111 PHY U58
Pin
M1
L3
L1
K3
Setting Description
PHYAddr 00111. Do not
advertise the PAUSE bit.
Auto-Neg en, advertise all
caps; prefer slave. Auto
crossover enabled.
125 MHz CLK option
disabled.
SGMII to Cu mode.
Fiber/copper auto-detect
disabled. Sleep mode
disabled.
MDC/MDIO selected.
Active Low interrupt. 50 Ω
SERDES option.
Name
MDIO_SDA
MDC_SCL
INT_B
RESET_B
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