Xilinx KCU105 User Manual page 64

Table 1-21: KCU105 Board GPIO Connections to FPGA U1 (Cont'd)
FPGA (U1)
Schematic Net Name
Pin
4-Pole DIP SW (Active High)
AN16
AN19
AP18
AN14
User Rotary Switch (Active High)
Y21
AD26
AF28
User GPIO SMA
G27
H27
Notes:
1. Routed through a 3.3V-to-1.8V level-shifter to FPGA.
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
(1)
GPIO_DIP_SW0
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
(1)
ROTARY_INCA
ROTARY_INCB
ROTARY_PUSH
USER_SMA_GPIO_N
USER_SMA_GPIO_P
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Chapter 1: KCU105 Evaluation Board Features
FPGA (U1)
I/O Standard
Direction
Input LVCMOS12
Input LVCMOS12
Input LVCMOS12
Input LVCMOS12
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
I/O LVCMOS18
I/O LVCMOS18
Device
SW12.4
SW12.3
SW12.2
SW12.1
SW13.1
SW13.6
SW13.5
J36.1
J36.1
64
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