Viterbi Decoding Support; Unsigned Integer Double-Precision Multiplication - Freescale Semiconductor SC140 DSP Core Reference Manual

DALU
Figure 2-11 illustrates the use of these instructions in the case of an unsigned integer double-precision
multiplication of 32-bit by 32-bit unsigned operands. In this example, only a 32-bit result is generated. The
most significant 32-bits are shifted out. All multiplications are of the "Unsigned x Unsigned" type using
different combinations of high and low portions.
impyuu d0,d1,d2
impyhluu d0,d1,d3
imaclhuu d0,d1,d3
aslw d3
add d2,d3
Figure 2-11. Unsigned Integer Double-Precision Multiplication

2.2.2.9 Viterbi Decoding Support

A set of DALU and AGU operations is provided for Viterbi decoding kernels. A special MAX2VIT
operation is defined. This instruction functions as a regular MAX2 instruction and is used to transfer two
16-bit maximum signed values. In addition, the MAX2VIT instruction updates two Viterbi flags (VFs)
which reside in the status register as described in
Complementary AGU move operations are provided (VSL instructions). For a full description of the
Viterbi instructions, see
2-30
Appendix A, "Viterbi Shift Left Move (AGU) VSL,"
D0.h
D1.h
Unsigned × Unsigned
Unsigned × Unsigned
×
D0.h D1.l
×
D1.h D0.l
D3.l
D3.h
Section 3.1.1, "Status Register (SR),"
D0.l D0.l
×
D1.l
=
×
D1.l D0.l
+
+
0
D3.l
32 bits
on page 3-1.
on page A-422.
SC140 DSP Core Reference Manual