Timing Of Three-Wire Serial I/O Mode; Serial Clock Selection And Application (In The Three-Wire Serial I/O Mode) - NEC PD750004 User Manual

µPD750008 USER'S MANUAL
SCK
SI
SO
IRQCSI
The SO pin becomes a CMOS output and outputs the state of the SO latch. So the output state of the
SO pin can be manipulated by setting the RELT bit and CMDT bit.
However, this manipulation must not be performed during serial transfer.
The output level of the SCK pin can be controlled by manipulating the P01 output latch in the output mode
(internal system clock mode). (See Section 5.6.8.)
(3) Serial clock selection
To select the serial clock, manipulate bits 0 and 1 of serial operation mode register 0 (CSIM). The serial
clock can be selected out of the following four clocks:
Table 5-7. Serial Clock Selection and Application (In the Three-Wire Serial I/O Mode)
Mode register
CSIM CSIM
1 0
0 0 External
SCK
0 1 TOUT
flip-flop
1 0 f
X
1 1 f
X
140
Figure 5-44. Timing of Three-Wire Serial I/O Mode
1 2
DI7 DI6
DO7 DO6
Transfer operation is started in phase with falling edge of SCK.
Execution of instruction that writes data to SIO (Transfer start request)
Serial clock
Masking of
Source
serial clock
Automatically
masked when
8-bit data
transfer is
completed
4
/2
3
/2
3 4 5
DI5 DI4 DI3
DO5 DO4 DO3
Timing for shift register R/W and
start of serial transfer
<1> In the operation halt mode
(CSIE = 0)
<2> When the serial clock is
masked after 8-bit transfer
<3> When SCK is high
6 7 8
DI2 DI1 DI0
DO2 DO1 DO0
Completion of transfer
Application
Slave CPU
Half-duplex asyn
chronous transfer
(software control)
Middle-speed
serial transfer
High-speed serial
transfer