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Xilinx RocketIO User Manual

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User Guide

UG024 (v1.5) October 16, 2002
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  • Page 1: User Guide

    RocketIO™ Transceiver User Guide UG024 (v1.5) October 16, 2002...
  • Page 2 All other trademarks are the property of their respective owners. Xilinx does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible.
  • Page 3 RocketIO™ Transceiver User Guide UG024 (v1.5) October 16, 2002 The following table shows the revision history for this document. Date Version Revision 11/20/01 Initial Xilinx release. 01/23/02 Updated for typographical and other errors found during review. 02/25/02 Part of Virtex-II Pro™ Developer’s Kit (March 2002 Release)
  • Page 4 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778...

  • Page 5: Table Of Contents

    RocketIO Features ........................13 In This User Guide ......................... 14 Naming Conventions ......................14 For More Information ......................14 Chapter 2: RocketIO Transceiver Overview Basic Architecture and Capabilities ................15 Clock Synthesizer ........................17 Clock and Data Recovery ..................... 18 Transmitter ..........................
  • Page 6 Deterministic Jitter (DJ) ......................87 Random Jitter (RJ) Clock and Data Recovery ..................... 87 PCB Design Requirements ....................89 Power Conditioning......................89 ......................89 Voltage Regulation ......................... 90 Passive Filtering www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 7 Epson EG-2121CA 2.5V (LVPECL outputs) ................... 94 Pletronics LV1145B (LVDS outputs) Other Important Design Notes ..................95 Powering the RocketIO Transceivers ................. 95 The POWERDOWN Port ..................... 95 Chapter 5: Simulation and Implementation Simulation Models ......................... 97 SmartModels .......................... 97 HSPICE ...........................
  • Page 8 UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 9: Schedule Of Figures

    Figures Chapter 1: Introduction Chapter 2: RocketIO Transceiver Overview Figure 2-1: RocketIO Transceiver Block Diagram ..............16 Figure 2-2: Clock Correction in Receiver ................. 21 Figure 2-3: Channel Bonding (Alignment) ................22 Chapter 3: Digital Design Considerations Figure 3-1: Two-Byte Clock ......................40 Figure 3-2: Four-Byte Clock ......................
  • Page 10 Figure 5-2: 2VP50 Implementation.................... 98 Appendix A: RocketIO Transceiver Timing Model Figure A-1: RocketIO Transceiver Block Diagram .............. 104 Figure A-2: RocketIO Transceiver Timing Relative to Clock Edge ........108 Appendix B: RocketIO Transceiver Cell Models www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™...

  • Page 11: Schedule Of Tables

    Chapter 1: Introduction Chapter 2: RocketIO Transceiver Overview Table 2-1: RocketIO Cores......................15 Table 2-2: Communications Standards Supported by RocketIO Transceiver ....15 Table 2-3: Serial Baud Rates and the SERDES_10B Attribute ..........16 Table 2-4: Supported RocketIO Transceiver Primitives............17 Table 2-5: Running Disparity Control ..................
  • Page 12 Table 5-4: LOOPBACK Modes....................102 Appendix A: RocketIO Transceiver Timing Model Table A-1: RocketIO Clock Descriptions ................103 Table A-2: Parameters Relative to the RX User Clock (RXUSRCLK) ....... 106 Table A-3: Parameters Relative to the RX User Clock2 (RXUSRCLK2) ......106 Table A-4: Parameters Relative to the TX User Clock2 (TXUSRCLK2)......

  • Page 13: Chapter 1: Introduction

    FALSE. Change the attribute name TERMINATION_IMP to RX_TERM_IMP. RocketIO Features The RocketIO™ transceiver’s flexible, programmable features allow a multi-gigabit serial transceiver to be easily integrated into any Virtex-II Pro design: • Variable speed full-duplex transceiver, allowing 622 Mb/s to 3.125 Gb/s baud transfer rates •...

  • Page 14: In This User Guide

    Naming Conventions Input and output ports of the RocketIO transceiver primitives are denoted in upper-case letters. Attributes of the RocketIO transceiver are denoted in upper-case letters with underscores. Trailing numbers in primitive names denote the byte width of the data path.

  • Page 15: Basic Architecture And Capabilities

    Chapter 2 RocketIO Transceiver Overview Basic Architecture and Capabilities The RocketIO transceiver is based on Mindspeed’s SkyRail™ technology. Figure 2-1, page 16, depicts an overall block diagram of the transceiver. Up to 24 transceiver modules are available on a single Virtex-II Pro FPGA, depending on the part being used.

  • Page 16: Figure 2-1: Rocketio Transceiver Block Diagram

    LOOPBACK[1:0] TXRESET RXRESET REFCLK REFCLK2 GNDA TX/RX GND REFCLKSEL BREFCLK AVCCAUXTX 2.5V TX BREFCLK2 RXUSRCLK VTTX Termination Supply TX RXUSRCLK2 TXUSRCLK TXUSRCLK2 DS083-2_04_090402 Figure 2-1: RocketIO Transceiver Block Diagram www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 17: Clock Synthesizer

    • Dynamic changes can be made by the ports of the primitives The RocketIO transceiver consists of the Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES), TX and RX buffers, clock generator, and clock recovery circuitry. The PCS contains the 8B/10B encoder/decoder and the elastic buffer supporting channel bonding and clock correction.

  • Page 18: Clock And Data Recovery

    Chapter 2: RocketIO Transceiver Overview Clock and Data Recovery The clock/data recovery (CDR) circuits lock to the reference clock automatically if the data is not present. For proper operation, frequency variations of REFCLK, TXUSRCLK, ± RXUSRCLK, and the incoming stream (RXRECCLK) must not exceed 100 ppm.

  • Page 19: Transmit Fifo

    Receiver Deserializer The RocketIO transceiver core accepts serial differential data on its RXP and RXN inputs. The clock/data recovery circuit extracts clock phase and frequency from the incoming data stream and re-times incoming data to this clock. The recovered clock is presented on output RXRECCLK at 1/20 of the received serial data rate.

  • Page 20: Receiver Termination

    Chapter 2: RocketIO Transceiver Overview Receiver Termination On-chip termination is provided at the receiver, eliminating the need for external termination. The receiver includes programmable on-chip termination circuitry for 50Ω (default) or 75Ω impedance. 8B/10B Decoder An optional 8B/10B decoder is included. A programmable option allows the decoder to be bypassed.

  • Page 21: Elastic And Transmitter Buffers

    If the byte sequence length is greater than one, and if attribute CLK_COR_REPEAT_WAIT is 0, then the transceiver can repeat the same sequence multiple times until the buffer is refilled to the half-full condition. UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 22: Channel Bonding

    Chapter 2: RocketIO Transceiver Overview Similarly, if RXUSRCLK is slower than RXRECCLK, the buffer fills up over time. The clock correction logic corrects for this by incrementing the read pointer to skip over a removable byte sequence that need not appear in the final FPGA core byte stream. This is shown in the...

  • Page 23: Transmitter Buffer

    The RocketIO transceiver CRC logic supports the 32-bit invariant CRC calculation used by Infiniband, FibreChannel, and Gigabit Ethernet. On the transmitter side, the CRC logic recognizes where the CRC bytes should be inserted and replaces four placeholder bytes at the tail of a data packet with the computed CRC.

  • Page 24: Table 2-7: Reset And Power Control Descriptions

    Chapter 2: RocketIO Transceiver Overview Additional reset and power control descriptions are given in Table 2-7 Table 2-8. Table 2-7: Reset and Power Control Descriptions Ports Description RXRESET Synchronous receive system reset recenters the receiver elastic buffer, and resets the 8B/10B decoder, comma detect, channel bonding, clock correction logic, and other receiver registers.

  • Page 25: Chapter 3: Digital Design Considerations

    Digital Design Considerations List of Available Ports The RocketIO transceiver primitives contain 50 ports, with the exception of the 46-port GT_ETHERNET and GT_FIBRE_CHAN primitives. The differential serial data ports (RXN, RXP, TXN, and TXP) are connected directly to external pads; the remaining 46 ports are all accessible from the FPGA logic (42 ports for GT_ETHERNET and GT_FIBRE_CHAN).
  • Page 26 RXNOTINTABLE 1, 2, 4 Status of encoded data when the data is not a valid character when asserted High. Applies to the byte-mapping scheme. Serial differential port (FPGA external) www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 27 Transmit data that can be 1, 2, or 4 bytes wide, depending on the primitive used. TXDATA [7:0] is always the last byte transmitted. The position of the first byte depends on selected TX data path width. UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...
  • Page 28 The port size changes with relation to the primitive selected, and also correlates to the byte mapping. External ports only accessible from package pins. Will be available in ISE 5.1. www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 29: Primitive Attributes

    Table 3-2 shows a brief description of each attribute. Table 3-3 Table 3-4 have the default values of each primitive. Table 3-2: RocketIO Transceiver Attributes Attribute Description ALIGN_COMMA_MSB TRUE/FALSE controls the alignment of detected commas within the transceiver’s 2-byte-wide data path.
  • Page 30 Chapter 3: Digital Design Considerations Table 3-2: RocketIO Transceiver Attributes (Continued) Attribute Description CHAN_BOND_OFFSET Integer 0-15 that defines offset (in bytes) from channel bonding sequence for realignment. It specifies the first elastic buffer read address that all channel- bonded transceivers have immediately after channel bonding.
  • Page 31 Primitive Attributes Table 3-2: RocketIO Transceiver Attributes (Continued) Attribute Description CLK_COR_KEEP_IDLE TRUE/FALSE controls whether or not the final byte stream must retain at least one clock correction sequence. FALSE: Transceiver can remove all clock correction sequences to further recenter the elastic buffer during clock correction.
  • Page 32 Chapter 3: Digital Design Considerations Table 3-2: RocketIO Transceiver Attributes (Continued) Attribute Description DEC_MCOMMA_DETECT TRUE/FALSE controls the raising of per-byte flag RXCHARISCOMMA on minus-comma. DEC_PCOMMA_DETECT TRUE/FALSE controls the raising of per-byte flag RXCHARISCOMMA on plus-comma. DEC_VALID_COMMA_ONLY TRUE/FALSE controls the raising of RXCHARISCOMMA on an invalid comma.

  • Page 33: Modifiable Primitives

    Modifiable Primitives Table 3-2: RocketIO Transceiver Attributes (Continued) Attribute Description RX_LOSS_OF_SYNC_FSM TRUE/FALSE denotes the nature of RXLOSSOFSYNC output. TRUE: RXLOSSOFSYNC outputs the state of the FSM bit. RXLOSSOFSYNC, page 26, for details. SERDES_10B Denotes whether the reference clock runs at 1/20 or 1/10 the serial bit rate.

  • Page 34: Table 3-3: Default Attribute Values: Gt_Aurora, Gt_Custom, Gt_Ethernet

    CRC_START_OF_PKT K27_7 K27_7 Note (7) DEC_MCOMMA_DETECT TRUE TRUE TRUE DEC_PCOMMA_DETECT TRUE TRUE TRUE DEC_VALID_COMMA_ONLY TRUE TRUE TRUE MCOMMA_10B_VALUE 1100000101 1100000000 1100000000 MCOMMA_DETECT TRUE TRUE TRUE PCOMMA_10B_VALUE 0011111010 0011111000 0011111000 www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 35 Table 3-4: Default Attribute Values: GT_FIBRE_CHAN, GT_INFINIBAND, and GT_XAUI Default Default Default Attribute GT_FIBRE_CHAN GT_INFINIBAND GT_XAUI ALIGN_COMMA_MSB FALSE FALSE FALSE CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT TRUE FALSE FALSE CHAN_BOND_SEQ_1_1 00000000000 00110111100 00101111100 UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...
  • Page 36 1111111000 CRC_END_OF_PKT Note (3) Note (3) K29_7 CRC_FORMAT FIBRE_CHAN INFINIBAND USER_MODE CRC_START_OF_PKT Note (3) Note (3) K27_7 DEC_MCOMMA_DETECT TRUE TRUE TRUE DEC_PCOMMA_DETECT TRUE TRUE TRUE DEC_VALID_COMMA_ONLY TRUE TRUE TRUE www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 37 Modifiable attribute for specific primitives. Depends on primitive used: either 1, 2, or 4. CRC_EOP and CRC_SOP are not applicable for this primitive. Will be available in ISE 5.1. UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 38: Byte Mapping

    REFCLK is connected to the REFCLK of the RocketIO transceiver. It also clocks a Digital Clock Manager (DCM) to generate all of the other clocks for the gigabit transceiver. Typically, TXUSRCLK = RXUSRCLK and TXUSRCLK2 = RXUSRCLK2.

  • Page 39: Clock Ratio

    Since CLK0 is needed for feedback, it can be used instead of CLK180 to clock USRCLK or USRCLK2 of the transceiver with the use of the transceiver’s local inverter, saving a global buffer (BUFG). UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 40: Example 1: Two-Byte Clock

    -- Components Declarations: component BUFG port ( I : in std_logic; O : out std_logic end component; component IBUFG port ( I : in std_logic; O : out std_logic www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 41 PSINCDEC => GND, PSEN => GND, PSCLK => GND, => RST, CLK0 => CLK0_W, LOCKED => LOCK -- BUFG Instantiation U_BUFG: IBUFG port map ( => REFCLKIN, => REFCLK UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 42: Chapter 3: Digital Design Considerations

    .CLK270 .CLK2X .CLK2X180 .CLKDV .CLKFX .CLKFX180 .LOCKED ( DCM_LOCKED ), .PSDONE .STATUS BUFG buf1 ( .I ( clk_i ), .O ( USRCLK_M ) IBUFG buf2( .I ( REFCLKIN ), www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 43: Example 2: Four-Byte Clock

    : in std_logic; USRCLK_M : out std_logic; USRCLK2_M : out std_logic; REFCLK : out std_logic; LOCK : out std_logic end FOUR_BYTE_CLK; architecture FOUR_BYTE_CLK_arch of FOUR_BYTE_CLK is -- Components Declarations: component BUFG UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...
  • Page 44 CLK0_W, DSSEN => GND, PSINCDEC => GND, PSEN => GND, PSCLK => GND, => RST, CLK0 => CLK0_W, CLKDV => CLKDV_W, LOCKED => LOCK -- BUFG Instantiation U_BUFG: IBUFG www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 45 ( REFCLKINBUF ) , .DSSEN 1'b0 ), .PSCLK ( 1'b0 ), .PSEN ( 1'b0 ), .PSINCDEC ( 1'b0 ), .RST ( 1'b0 ), .CLK0 ( clk_i ), .CLK90 .CLK180 .CLK270 .CLK2X UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 46: Example 3: One-Byte Clock

    VHDL submodule DCM for 1-byte GT -- Device: Virtex-II Pro Family --------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on entity ONE_BYTE_CLK is www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 47 : out std_logic_vector ( 7 downto 0 ) end component; -- Signal Declarations: signal GND : std_logic; signal CLK0_W : std_logic; signal CLK1X_W : std_logic; signal CLK2X180_W : std_logic; begin <= '0'; UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...
  • Page 48 DCM for 1-byte GT // Device: Virtex-II Pro Family module ONE_BYTE_CLK ( REFCLKIN, REFCLK, USRCLK_M, USRCLK2_M, DCM_LOCKED input REFCLKIN; output REFCLK; output USRCLK_M; output USRCLK2_M; output DCM_LOCKED; wire REFCLKIN; www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 49 .I ( clk2x_180 ), .O ( USRCLK2_M ) BUFG buf2 ( .I ( clk_i ), .O ( USRCLK_M ) IBUFGbuf3 ( .I ( REFCLKIN ), .O ( REFCLKINBUF ) endmodule UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 50: Brefclk

    BREFCLK At speeds of 2.5 Gb/s or greater, the REFCLK configuration introduces more than the maximum allowable jitter to the RocketIO transceiver. For these higher speeds, the BREFCLK configuration is required. The BREFCLK configuration uses dedicated routing resources that reduce jitter.

  • Page 51: Table 3-9: Brefclk Pin Numbers

    W11/Y11 Y12/W12 FF672 B14/C14 C13/B13 AD14/AE14 AE13/AD13 FF896 F16/G16 G15/F15 AH16/AJ16 AJ15/AH15 FF1152 H18/J18 J17/H17 AK18/AL18 AL17/AK17 FF1148 FF1517 E20/D20 J20/K20 AR20/AT20 AL20/AK20 FF1704 G22/F22 F21/G21 AU22/AT22 AT21/AU21 FF1696 UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 52: Half-Rate Clocking Scheme

    Figure 3-6: Two-Byte Data Path Clocks, SERDES_10B = TRUE Clocks for 4-Byte Data Path (SERDES_10B = TRUE) REFCLK TXUSRCLK RXUSRCLK TXUSRCLK2 RXUSRCLK2 UG024_31_051302 Figure 3-7: Four-Byte Data Path Clocks, SERDES_10B = TRUE www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 53: Multiplexed Clocking Scheme

    DCMs. The clocks are then multiplexed before input into the RocketIO transceiver. User logic can be designed to determine during autonegotiation if the reference clock used for the transceiver is incorrect.

  • Page 54: Receiver Latency

    UNISIM.VCOMPONENTS.ALL; -- pragma translate_on entity gt_reset is port ( USRCLK2_M : in std_logic; LOCK : in std_logic; REFCLK : out std_logic; DCM_LOCKED: in std_logic; : out std_logic); end gt_reset; www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 55 <= startup_counter + 1; always @ ( posedge USRCLK2_M or negedge DCM_LOCKED ) if ( !DCM_LOCKED ) RST <= 1'b1; else RST <= ( startup_counter != 8'h02 ); endmodule UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 56: Rocketio Transceiver Instantiations

    Elastic buffer skipped one clock correction sequence for current RXDATA Elastic buffer skipped two clock correction sequence for current RXDATA Elastic buffer skipped three clock correction sequence for current RXDATA www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 57: Rx_Loss_Of_Sync_Fsm

    (alignment) sequence has just been written into the elastic buffer. 8B/10B Operation The RocketIO transceiver has the ability to encode eight bits into a 10-bit serial stream using standard 8B/10B encoding. This guarantees a DC-balanced, edge-rich serial stream, facilitating DC- or AC-coupling and clock recovery. If the 8B/10B encoding is disabled, the data is sent through in 10-bit blocks.

  • Page 58: Figure 3-9: 8B/10B Data Flow

    ( or: [1] / [2] / [3] ) RXRUNDISP[0], ( or: [1] / [2] / [3] ) Indicates running disparity is POSITIVE RXDATA[7:0] ( or: [15:8] / [23:16] / [31:24] ) www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 59: Vitesse Disparity Example

    K28.5- K28.5- K28.5+ K28.5+ Instead of: K28.5+ K28.5- K28.5+ K28.5- K28.5- K28.5+ K28.5- K28.5+ The logic must assert TXCHARDISPVAL to cause the serial data to send out two negative running disparity characters. UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 60: Transmitting Vitesse Channel Bonding Sequence

    K28.5- (or K28.5+) 0 1 0 1 10111100 K28.5- (or K28.5+) The RocketIO core receives this data but must have the CHAN_BOND_SEQ set with the disp_err bit set High for the cases when TXCHARDISPVAL is set High during data transmission.

  • Page 61: Status Signals

    100011 0100 D18.0 000 10010 010011 1011 010011 0100 D19.0 000 10011 110010 1011 110010 0100 D20.0 000 10100 001011 1011 001011 0100 D21.0 000 10101 101010 1011 101010 0100 UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...
  • Page 62 010011 1001 D19.1 001 10011 110010 1001 110010 1001 D20.1 001 10100 001011 1001 001011 1001 D21.1 001 10101 101010 1001 101010 1001 D22.1 001 10110 011010 1001 011010 1001 www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 63 110010 0101 D20.2 010 10100 001011 0101 001011 0101 D21.2 010 10101 101010 0101 101010 0101 D22.2 010 10110 011010 0101 011010 0101 D23.2 010 10111 111010 0101 000101 0101 UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...
  • Page 64 001011 0011 D21.3 011 10101 101010 1100 101010 0011 D22.3 011 10110 011010 1100 011010 0011 D23.3 011 10111 111010 0011 000101 1100 D24.3 011 11000 110011 0011 001100 1100 www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 65 101010 0010 D22.4 100 10110 011010 1101 011010 0010 D23.4 100 10111 111010 0010 000101 1101 D24.4 100 11000 110011 0010 001100 1101 D25.4 100 11001 100110 1101 100110 0010 UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...
  • Page 66 011010 1010 D23.5 101 10111 111010 1010 000101 1010 D24.5 101 11000 110011 1010 001100 1010 D25.5 101 11001 100110 1010 100110 1010 D26.5 101 11010 010010 1010 010110 1010 www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 67 000101 0110 D24.6 110 11000 110011 0110 001100 0110 D25.6 110 11001 100110 0110 100110 0110 D26.6 110 11010 010010 0110 010110 0110 D27.6 110 11011 110110 0110 001001 0110 UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...
  • Page 68 001100 1110 D25.7 111 11001 100110 1110 100110 0001 D26.7 111 11010 010110 1110 010110 0001 D27.7 111 11011 110110 0001 001001 1110 D28.7 111 11100 001110 1110 001110 0001 www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 69: 8B/10B Serial Output Format

    Table 3-13. Parallel 8B/10B Serial First transmitted Last transmitted UG024_10_021102 Figure 3-12: 8B/10B Parallel to Serial Conversion UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 70: Hdl Code Examples: Transceiver Bypassing Of 8B/10B Encoding

    CRC, to test the CRC error logic. CRC Generation RocketIO transceivers support a 32-bit invariant CRC (fixed 32-bit polynomial shown below) for Gigabit Ethernet, Fibre Channel, Infiniband, and user-defined modes. The CRC recognizes the SOP (Start of Packet), EOP (End of Packet), and other packet features to identify the beginning and end of data.

  • Page 71: Crc Latency

    CRC Enabled CRC Limitations There are several limitations to the RocketIO CRC. First, CRC is not supported in byte- striped data. If byte-striped (channel bonding) is required, CRC must be computed in CLBs prior to the byte-striping. The CRC support of Infiniband is incomplete, because the 16-bit variant CRC must be done in the CLBs making the transceiver core CRC function redundant.

  • Page 72: Fibrechannel

    /K28.5/D21.5/ or /K28.5/D10.5/. When the RocketIO CRC determines that the running disparity must be inverted to satisfy Fibre Channel requirements, it will convert the second byte of the EOF frame delimiter (D21.4 or D10.4) to the value required to invert the running disparity (D21.5 or D10.5).

  • Page 73: Channel Bonding (Channel-To-Channel Alignment)

    "channels." Among these primitives are GT_CUSTOM, GT_INFINIBAND, GT_XAUI, and GT_AURORA. To "bond" channels together, there is always one "master." The other channels can either be a SLAVE_1_HOP or SLAVE_2_HOPs. SLAVE_1_HOP is a slave to a UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 74: Hdl Code Examples: Channel Bonding

    ENCHANSYNC Dynamic control as desired Tie High HDL Code Examples: Channel Bonding Code examples can be downloaded from the Virtex-II Pro Platform FPGA Handbook page on the Xilinx website. Go to: http://www.xilinx.com/publications/products/v2pro/handbook/index.htm www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 75: Other Important Design Notes

    Other Important Design Notes Receive Data Path 32-bit Alignment The RocketIO transceiver uses the attribute ALIGN_COMMA_MSB to align protocol delimiters with the use of comma characters (special K characters K28.5, K28.1, and K28.7 for most protocols). Setting the ALIGN_COMMA_MSB to TRUE/FALSE determines where the comma characters appear on the RXDATA bus.

  • Page 76: 32-Bit Alignment Design

    RXCHARISCOMMA for comma detection. Verilog /********************************************************************* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.
  • Page 77 // aligned_data[31:0] -- Properly aligned 32-bit ALIGNED_DATA // sync -- Indicator that aligned_data is properly aligned // aligned_rxisk[3:0] - poperly aligned 4 bit RXCHARISK // Inputs - These are all RocketIO inputs or outputs // as indicated: // usrclk2 -- RXUSRCLK2...
  • Page 78 @ ( posedge usrclk2 or posedge rxreset ) begin if ( rxreset ) begin rxdata_reg <= 16'h0000; aligned_data <= 32'h0000_0000; www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 79: Vhdl

    -- * -- *********************************************************** -- *********************************************************** -- * -- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -- * SOLUTIONS FOR XILINX DEVICES.
  • Page 80 -- aligned_data[31:0] -- Properly aligned 32-std_logic ALIGNED_DATA -- sync -- Indicator that aligned_data is properly aligned -- aligned_rxisk[3:0] -properly aligned 4-std_logic RXCHARISK -- Inputs - These are all RocketIO inputs or outputs -- as indicated: -- usrclk2 -- RXUSRCLK2 -- rxreset -- RXRESET...
  • Page 81 IF ((rxreset OR rxrealign) = '1') THEN sync_hold <= '0'; ELSE IF (wait_to_sync = "0000")THEN IF ((rxchariscomma3 OR rxchariscomma1) = '1') THEN sync_hold <= '1'; END IF; END IF; END IF; END IF; UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...
  • Page 82 <= '1'; ELSE rxdata_hold(31 DOWNTO 0) <= rxdata(31 DOWNTO 0); rxisk_hold(3 DOWNTO 0) <= rxisk(3 DOWNTO 0); END IF; END IF; END IF; END PROCESS; END ARCHITECTURE translated; www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 83: Serial I/O Description

    DATA CML Output Driver U024_06_020802 Figure 4-1: Differential Amplifier The RocketIO transceiver is implemented in Current Mode Logic (CML). A CML output consists of transistors configured as shown in Figure 4-1. CML uses a positive supply and offers easy interface requirements. In this configuration, both legs of the driver, V and V sink current, with one leg always sinking more current than its complement.

  • Page 84: Pre-Emphasis Techniques

    LOGIC or normal level (i.e., no pre-emphasis). A second characteristic of RocketIO transceiver pre-emphasis is that the STRONG level is reduced after some time to the LOGIC level, thereby minimizing the voltage swing necessary to switch the differential pair into the opposite state.

  • Page 85: Figure 4-2: Alternating K28.5+ With No Pre-Emphasis

    Pre-emphasis Techniques UG024_17_020802 Figure 4-2: Alternating K28.5+ with No Pre-Emphasis Logic High Strong High Logic Low Strong Low UG024_18_020802 Figure 4-3: K28.5+ with Pre-Emphasis UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 86: Figure 4-5: Eye Diagram, 33% Pre-Emphasis

    Chapter 4: Analog Design Considerations ug024_36_091802 Figure 4-4: Eye Diagram, 10% Pre-Emphasis ug024_37_091802 Figure 4-5: Eye Diagram, 33% Pre-Emphasis www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 87: Differential Receiver

    The serial transceiver input is locked to the input data stream through Clock and Data Recovery (CDR), a built-in feature of the RocketIO transceiver. CDR keys off the rising and falling edges of incoming data and derives a clock that is representative of the incoming data rate.

  • Page 88: Table 4-4: Cdr Parameters

    FIFO. The FIFO depth accounts for the slight phase difference between these two clocks. If the clocks are locked in frequency, then the FIFO acts much like a pass-through buffer. www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 89: Pcb Design Requirements

    Xilinx, Inc. Power Conditioning Each RocketIO transceiver has five power supply pins, all of which are sensitive to noise. Table 4-5, summarizes the power supply pins, their names, associated voltages, and power requirements.

  • Page 90: Passive Filtering

    1.8 V to 2.625 V. In cases where the RocketIO transceiver is interfacing with a transceiver from another vendor, termination voltage may be dictated by the specifications of the other transceiver.

  • Page 91: High-Speed Serial Trace Design

    High-Speed Serial Trace Design Routing Serial Traces All RocketIO transceiver I/Os are placed on the periphery of the BGA package to facilitate routing and inspection (since JTAG is not available on serial I/O pins). Two output/input impedance options are available in the RocketIO transceivers: 50Ω and 75Ω. Controlled UG024 (v1.5) October 16, 2002...

  • Page 92: Differential Trace Design

    PCB routes carry especially noisy signals, such as TTL and other similarly noisy standards. The RocketIO transceiver is designed to function at 3.125 Gb/s through 20 inches of FR4 with two high-bandwidth connectors. Longer trace lengths require either a low-loss dielectric or considerably wider serial traces.

  • Page 93: Ac And Dc Coupling

    Some designs require AC coupling to accommodate hot plug-in, and/or differing power supply voltages at different transceivers. This is illustrated in Figure 4-13. 0DIFF UG024_23_020802 Figure 4-13: AC-Coupled Serial Link UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 94: Reference Clock

    8B/10B encoding is used. Different data rates and different encoding schemes may require a different value. DC coupling (direct connection) is preferable in cases where RocketIO transceivers are interfaced with other RocketIO transceivers or other Mindspeed transceivers that have compatible differential and common mode voltage specifications.

  • Page 95: Other Important Design Notes

    Other Important Design Notes Powering the RocketIO Transceivers IMPORTANT! All RocketIO transceivers in the FPGA, whether instantiated in the design or not, must be connected to power and ground. Unused transceivers may be powered by any 2.5 V source, and passive filtering is not required. Refer to...
  • Page 96 Chapter 4: Analog Design Considerations www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 97: Chapter 5: Simulation And Implementation

    (16) per chip. To ensure the timing is met on the link between the CHBONDO and CHBONDI ports, a constraint must be added to check the time delay. The UCF example below shows and describes this. UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 98: Ucf Example

    6.4 ns – 0.2 ns – 2.0 ns = 4.2 ns This design used four RocketIO multi-gigabit transceivers, consisting of one master, two Slave_1_hop, and one Slave_2_hops. The net chbond_m_s01[3:0] connects the master and two Slave_1_hop. The net chbond_s1_s2[3:0] connects one Slave_1_hop and one Slave_2_hops.

  • Page 99: Mgt Package Pins

    A18, A17 A19, A18 A27, A26 A27, A26 GT_X2_Y0 AK14, AK13, AK14, AK13, AP17, AP16, AP21, AP20, AP25, AP24, AK12, AK11 AK12, AK11 AP15, AP14 AP19, AP18 AP23, AP22 UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 100: Table 5-3: Loc Grid & Package Pins Correlation For Ff1517 And Ff1704

    AW30, AW29 AW30, AW29 BB35, BB34 BB39, BB38 GT_X1_Y1 A32, A31, A32, A31, A32, A31, A37, A36, A41, A40, A30, A29 A30, A29 A30, A29 A35, A34 A39, A38 www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...
  • Page 101 BB9, BB8, AW5, AW4 BB3, BB2 BB7, BB6 GT_X9_Y1 A7, A6, A5, A5, A4, A3, A9, A8, A7, GT_X10_Y0 BB5, BB4, BB3, BB2 GT_X10_Y1 A5, A4, A3, GT_X11_Y0 GT_X11_Y1 UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 102: Diagnostic Signals

    Chapter 5: Simulation and Implementation Diagnostic Signals Often a diagnostic check is needed upon power-up. RocketIO transceivers have several inputs and outputs to run these checks. LOOPBACK LOOPBACK allows the user to send the data that is being transmitted directly to the receiver of the transceiver.

  • Page 103: Appendix A: Rocketio Transceiver Timing Model

    RocketIO core logic are ignored. Signals are characterized with setup and hold times for inputs, and with clock to valid output times for outputs. There are five clocks associated with the RocketIO core, but only three of these clocks— RXUSRCLK, RXUSRCLK2, and TXUSRCLK2—have I/Os that are synchronous to them.

  • Page 104: Timing Parameters

    Appendix A: RocketIO Transceiver Timing Model PACKAGE PINS MULTI-GIGABIT TRANSCEIVER CORE FPGA FABRIC AVCCAUXRX Power Down 2.5V RX POWERDOWN RXRECCLK VTRX Termination Supply RX RXPOLARITY RXREALIGN RXCOMMADET ENPCOMMAALIGN ENMCOMMAALIGN RXCHECKINGCRC Check RXCRCERR RXDATA[15:0] RXDATA[31:16] RXNOTINTABLE[3:0] Comma Elastic RXDISPERR[3:0] Detect Deserializer...

  • Page 105: Setup/Hold Times Of Inputs Relative To Clock

    Setup/Hold Times of Inputs Relative to Clock Basic Format: ParameterName_SIGNAL where ParameterName = T with subscript string defining the timing relationship SIGNAL name of RocketIO signal synchronous to the clock ParameterName Format: Setup time before clock edge GxCK Hold time after clock edge GCKx where...

  • Page 106: Timing Parameter Tables And Diagram

    The following four tables list the timing parameters as reported by the implementation tools relative to the clocks given in Table A-1, along with the RocketIO signals that are synchronous to each clock. (No signals are synchronous to REFCLK or TXUSRCLK.) A timing diagram (Figure A-2) illustrates the timing relationships.

  • Page 107: Table A-4: Parameters Relative To The Tx User Clock2 (Txusrclk2)

    Clock pulse width, High state TXUSRCLK TXPWH Clock pulse width, Low state TXUSRCLK TXPWL Notes: REFCLK is not synchronous to any RocketIO signals. TXUSRCLK is not synchronous to any RocketIO signals. UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide...

  • Page 108: Figure A-2: Rocketio Transceiver Timing Relative To Clock Edge

    GWL x GWH CLOCK GCCK GCKC CONTROL INPUTS GCKCO CONTROL OUTPUTS GCKDO DATA OUTPUTS GDCK GCKD DATA INPUTS UG012_106_02_100101 Figure A-2: RocketIO Transceiver Timing Relative to Clock Edge www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

  • Page 109: Summary

    Summary This appendix documents the RocketIO™ Multi-Gigabit Transceiver cell models. The following information lists the Verilog module declarations of the model and pins associated with each of the RocketIO communication standards available in the Virtex-II Pro family. Verilog Module Declarations...

  • Page 110: Gt_Aurora_2

    Appendix B: RocketIO Transceiver Cell Models BREFCLK2, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2 GT_AURORA_2 module GT_AURORA_2 ( CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR,...

  • Page 111: Gt_Aurora_4

    RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, BREFCLK, BREFCLK2, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 112: Gt_Custom

    Appendix B: RocketIO Transceiver Cell Models TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2 GT_CUSTOM module GT_CUSTOM ( CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP,...

  • Page 113: Gt_Ethernet_1

    TXN, TXP, TXRUNDISP, CONFIGENABLE, CONFIGIN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, BREFCLK, BREFCLK2, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2 UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 114: Gt_Ethernet_2

    Appendix B: RocketIO Transceiver Cell Models GT_ETHERNET_2 module GT_ETHERNET_2 ( CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, CONFIGENABLE, CONFIGIN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, BREFCLK, BREFCLK2, RXN,...

  • Page 115: Gt_Fibre_Chan_1

    TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2 GT_FIBRE_CHAN_1 module GT_FIBRE_CHAN_1 ( CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 116: Gt_Fibre_Chan_2

    Appendix B: RocketIO Transceiver Cell Models RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, CONFIGENABLE, CONFIGIN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, BREFCLK, BREFCLK2, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2 GT_FIBRE_CHAN_2 module GT_FIBRE_CHAN_2 (...

  • Page 117: Gt_Fibre_Chan_4

    RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, CONFIGENABLE, CONFIGIN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, BREFCLK, BREFCLK2, RXN, RXP, RXPOLARITY, UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 118: Gt_Infiniband_1

    Appendix B: RocketIO Transceiver Cell Models RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2 GT_INFINIBAND_1 module GT_INFINIBAND_1 ( CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK,...

  • Page 119: Gt_Infiniband_2

    RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, BREFCLK, BREFCLK2, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 120: Gt_Infiniband_4

    Appendix B: RocketIO Transceiver Cell Models TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2 GT_INFINIBAND_4 module GT_INFINIBAND_4 ( CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, CHBONDI, CONFIGENABLE,...

  • Page 121: Gt_Xaui_1

    TXRUNDISP, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, BREFCLK, BREFCLK2, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2 UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...

  • Page 122: Gt_Xaui_2

    Appendix B: RocketIO Transceiver Cell Models GT_XAUI_2 module GT_XAUI_2 ( CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, LOOPBACK, POWERDOWN, REFCLK, REFCLK2,...
  • Page 123 TXRUNDISP, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, BREFCLK, BREFCLK2, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2 UG024 (v1.5) October 16, 2002 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...
  • Page 124 Appendix B: RocketIO Transceiver Cell Models www.xilinx.com UG024 (v1.5) October 16, 2002 1-800-255-7778 RocketIO™ Transceiver User Guide...

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