Tx Buffer - Xilinx Virtex UltraScale+ FPGAs User Manual

Proprietary Backplane Protocols with FEC up to 58 Gb/s
FEC can be enabled in 50G raw mode (with or without scrambling).

TX Buffer

The GTM transceiver TX datapath has two internal parallel clock domains used in the PCS: the
interface with PMA parallel clock domian (XCLK), and the PCS internal clock domain
(TXUSRCLK). To transmit data, the TX buffer provides data width conversion between these
clock domains when necessary, depending on the operating data width and encoding mode. The
following figure shows the TX datapath clock domains.
TX Serial Clock
TX
Pre/
TX Pre
PISO
Driver 2/
Post
Emp
TX PMA
The GTM transmitter includes a TX FIFO to support data width conversion when data crosses
from TXUSRCLK to XCLK domain, and the table below shows the possible scenarios. The buffer
does not tolerate ppm differences, and only provides phase compensation between the two
clocks. The TX buffer inside the GTM transceiver must always be used. Buffer bypass is not
allowed.
Table 34: TX FIFO Data Width Conversion Scenarios
PCS Parallel Clock (TXUSRCLK)
Domain Data Width
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Figure 30:
PMA Parallel Clock (XCLK)
Pre- Gray
Coder Encoder
TX PCS
To RX Parallel Data
(Near-End PCS Loopback)
64-bit
80-bit
128-bit
TX Clock Domains
Pattern
Generator
TX
Polarity
FIFO
PMA Parallel Clock (XCLK) Domain
Data Width
64-bit
128-bit
128-bit
Send Feedback
Chapter 3: Transmitter
Device Parallel
PCS Parallel Clock (TXUSRCLK)
(TXUSRCLK2)
FEC
Interface
From RX Parallel Data
(Far-End PCS Loopback)
FEC Support
No
Yes
No
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Clock
TX
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