Preface: About This Guide; Guide Contents - Xilinx Virtex-5 RocketIO GTP User Manual

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About This Guide
This document shows how to use the RocketIO™ GTP transceivers in Virtex™-5 FPGAs.
Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on
the Xilinx website at http://www.xilinx.com/virtex5.

Guide Contents

This manual contains the following chapters and appendices:
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Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
"Section 1: FPGA Level Design"
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Chapter 1, "Introduction to the RocketIO GTP Transceiver"
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Chapter 2, "RocketIO GTP Transceiver Wizard"
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Chapter 3, "Simulation"
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Chapter 4, "Implementation"
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Chapter 5, "Tile Features"
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Chapter 6, "GTP Transmitter (TX)"
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Chapter 7, "GTP Receiver (RX)"
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Chapter 8, "Cyclic Redundancy Check (CRC)"
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Chapter 9, "Loopback"
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Chapter 10, "GTP-to-Board Interface"
"Section 2: Board Level Design"
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Chapter 11, "Design Constraints Overview"
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Chapter 12, "PCB Materials and Traces"
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Chapter 13, "Design of Transitions"
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Chapter 14, "Guidelines and Examples"
"Section 3: Appendices"
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Appendix A, "MGT to GTP Transceiver Design Migration"
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Appendix B, "OOB/Beacon Signaling"
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Appendix C, "8B/10B Valid Characters"
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Appendix D, "DRP Address Map of the GTP_DUAL Tile"
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Appendix E, "Low Latency Design"
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Preface
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