Revision Id (Rev Id) Register - Intel 21555 User Manual

Table 62. Primary and Secondary Status Registers
The bits described in
and of the secondary interface for the Secondary Status register. W1TC indicates that writing a 1 to that bit
clears the bit to 0. Writing a 0 has no effect.
Offsets
Primary byte
Secondary byte
Bit Name
Data Parity
8
Detected
10:9 DEVSEL# timing
Signaled Target
11
Abort
Received Target
12
Abort
Received Master
13
Abort
Signaled System
14
Error
Detected Parity
15
Error
Table 63. Revision ID (Rev ID) Register
• Primary byte offset: 08h and 48h
• Secondary byte offset: 08h and 48h
Bit Name
7:0 Revision ID
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Table 62 reflect the status of the 21555 primary interface for the Primary Status register,
Primary Status
07:06h
47:46h
R/W Description
This bit is set to a 1 when all of the following are true:
• The 21555 is a master on the corresponding bus.
• PERR# is detected asserted for writes or a parity error is detected
R/
for reads.
W1TC
• Parity Error Response bit is set in the Primary or Secondary
Command register.
Reset value is 0.
Indicates slowest response to a non configuration command on the
R corresponding interface. Reads as 01b to indicate that the 21555
responds no slower than with medium timing.
This bit is set to a 1 when the 21555 is acting as a target on the
R/
corresponding bus and returns a target abort to the initiator.
W1TC
Reset value is 0.
This bit is set to a 1 when the 21555 is acting as an initiator on the
R/
corresponding bus and receives a target abort.
W1TC
Reset value is 0.
This bit is set to a 1 when the 21555 is acting as an initiator on the
R/
corresponding bus and detects a master abort.
W1TC
Reset value is 0.
This bit is set to a 1 when the 21555 has asserted SERR# on the
R/
corresponding bus.
W1TC
Reset value is 0.
This bit is set to a 1 when the 21555 detects an address or data parity
R/
error on the corresponding interface.
W1TC
Reset value is 0.
R/W Description
This register indicates the revision number of this device. The initial revision
R
reads as 0. Subsequent revisions increment by 1.
(Sheet 2 of 2)
Secondary Status
47:46h
07:06h
List of Registers
151