I/O Memory Details - Omron CP1L Operation Manual

Specifications
2-2-2

I/O Memory Details

Type
Model CP1L-M60DR-A
CP1L-M60DR-D
CP1L-M60DT-A
CP1L-M60DT-D
CP1L-M60DT1-D
I/O Input bits 36 bits
Areas CIO 0.00 to
CIO 0.11
CIO 1.00 to
CIO 1.11
CIO 2.00 to
CIO 2.11
Output 24 bits
bits CIO 100.00 to
CIO 100.07
CIO 101.00 to
CIO 101.07
CIO 102.00 to
CIO 102.07
1:1 Link 1,024 bits (64 words): CIO 3000.00 to CIO 3063.15 (words CIO 3000 to CIO 3063)
Bit Area
Serial PLC 1,440 bits (90 words): CIO 3100.00 to CIO 3189.15 (words CIO 3100 to CIO 3189)
Link Area
Work bits 4,800 bits (300 words): CIO 1200.00 to CIO 1499.15 (words CIO 1200 to CIO 1499)
6,400 bits (400 words): CIO 1500.00 to CIO 1899.15 (words CIO 1500 to CIO 1899)
15,360 bits (960 words): CIO 2000.00 to CIO 2959.15 (words CIO 2000 to CIO 2959)
9,600 bits (600 words): CIO 3200.00 to CIO 3799.15 (words CIO 3200 to CIO 3799)
37,504 bits (2,344 words): CIO 3800.00 to CIO 6143.15 (words CIO 3800 to CIO 6143)
Work bits 8,192 bits (512 words): W000.00 to W511.15 (words W0 to W511)
TR Area 16 bits: TR0 to TR15
HR Area 24,576 bits (1,536 words): H0.00 to H1535.15 (words H0 to H1535)
AR Area Read-only (Write-prohibited) 7,168 bits (448 words): A0.00 to A447.15 (words A0 to A447)
Read/Write 8,192 bits (512 words): A448.00 to A959.15 (words A448 to A959)
Timers 4,096 bits: T0 to T4095
Counters 4,096 bits: C0 to C4095
DM Area 32 Kwords: D0 to D32767
Note Initial data can be transferred to the CPU
DM fixed allocation words for Modbus-RTU Easy
Master
D32200 to D32249 for Serial Port 1, D32300 to
D32349 for Serial Port 2
Data Register 16 registers (16 bits): DR0 to DR15
Area
Index Register 16 registers (16 bits): IR0 to IR15
Area
Task Flag Area 32 flags (32 bits): TK0 to TK31
Trace Memory 4,000 words (500 samples for the trace data maximum of 31 bits and 6 words.)
50
M CPU Units
CP1L-M40DR-A
CP1L-M40DR-D
CP1L-M40DT-A
CP1L-M40DT-D
CP1L-M40DT1-D
24 bits
CIO 0.00 to
CIO 0.11
CIO 1.00 to
CIO 1.11
16 bits
CIO 100.00 to
CIO 100.07
CIO 101.00 to
CIO 101.07
Unit's built-in flash memory using the data
memory initial data transfer function. A set-
ting in the PLC Setup can be used so that
the data in flash memory is transferred to
RAM at startup.
CP1L-M30DR-A CP1L-L20DR-A
CP1L-M30DR-D CP1L-L20DR-D
CP1L-M30DT-A CP1L-L20DT-A
CP1L-M30DT-D CP1L-L20DT-D
CP1L-M30DT1-D CP1L-L20DT1-D
CP1L-J20DR-A
CP1L-J20DR-D
CP1L-J20DT1-D
18 bits 12 bits
CIO 0.00 to CIO 0.00 to
CIO 0.11 CIO 0.11
CIO 1.00 to
CIO 1.05
12 bits 8 bits
CIO 100.00 to CIO 100.00 to
CIO 100.07 CIO 100.07
CIO 101.00 to
CIO 100.03
10 Kwords: D0 to D9999 and D32000 to D32767
Note Initial data can be transferred to the CPU
Unit's built-in flash memory using the data
memory initial data transfer function. A set-
ting in the PLC Setup can be used so that
the data in flash memory is transferred to
RAM at startup.
DM fixed allocation words for Modbus-RTU Easy
Master
D32300 to D32349 for Serial Port 1
Section 2-2
L CPU Units
CP1L-L14DR-A CP1L-L10DR-A
CP1L-L14DR-D CP1L-L10DR-D
CP1L-L14DT-A CP1L-L10DT-A
CP1L-L14DT-D CP1L-L10DT-D
CP1L-L14DT1-D CP1L-L10DT1-D
CP1L-J14DR-A
CP1L-J14DR-D
CP1L-J14DT1-D
8 bits 6 bits
CIO 0.00 to CIO 0.00 to
CIO 0.07 CIO 0.05
6 bits 4 bits
CIO 100.00 to CIO 100.00 to
CIO 100.05 CIO 100.03
Not Support
Not Support